5889f02032
The timer structure (in particular, the offset to memory addresses) on recent MTK SoCs for example MT8195 has been changed. BUG=b:195274787 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifd6ff65a825c4309c47f3b115b80a8ecd42fedac Reviewed-on: https://review.coreboot.org/c/coreboot/+/56845 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
94 lines
2.2 KiB
Plaintext
94 lines
2.2 KiB
Plaintext
##
|
|
##
|
|
## SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
choice
|
|
prompt "Timer driver"
|
|
default TIMER_NONE if !ARCH_X86
|
|
default TIMER_RDTSC if ARCH_X86
|
|
|
|
config TIMER_RDTSC
|
|
bool "x86 rdtsc"
|
|
depends on ARCH_X86
|
|
|
|
config TIMER_NONE
|
|
bool "None"
|
|
help
|
|
The timer driver is provided by the payload itself.
|
|
|
|
config TIMER_MCT
|
|
bool "Exynos MCT"
|
|
|
|
config TIMER_TEGRA_1US
|
|
bool "Tegra 1us"
|
|
|
|
config TIMER_IPQ806X
|
|
bool "Timer for ipq806x platforms"
|
|
|
|
config TIMER_IPQ40XX
|
|
bool "Timer for ipq40xx platforms"
|
|
help
|
|
This is the timer driver for QCA IPQ40xx based
|
|
platforms.
|
|
|
|
config TIMER_ARM64_ARCH
|
|
bool "Architecture Timer for ARM64 platforms"
|
|
help
|
|
The cntfrq register needs to have been pre-initialized.
|
|
|
|
config TIMER_RK3288
|
|
bool "Timer for Rockchip RK3288"
|
|
|
|
config TIMER_RK3399
|
|
bool "Timer for Rockchip RK3399"
|
|
|
|
config TIMER_MTK
|
|
bool "Timer for MediaTek"
|
|
|
|
config TIMER_MTK_V2
|
|
bool "Timer for MediaTek V2"
|
|
|
|
endchoice
|
|
|
|
config TIMER_GENERIC_HZ
|
|
int "Generic Timer Frequency"
|
|
default 48000000 if TIMER_IPQ40XX
|
|
default 6250000 if TIMER_IPQ806X
|
|
default 24000000 if TIMER_MCT
|
|
default 13000000 if TIMER_MTK
|
|
default 13000000 if TIMER_MTK_V2
|
|
default 24000000 if TIMER_RK3288
|
|
default 24000000 if TIMER_RK3399
|
|
default 1000000 if TIMER_TEGRA_1US
|
|
default 0
|
|
help
|
|
Clock frequency of generic time counter in Hertz. Leave at 0 to
|
|
disable when using a non-generic timer driver.
|
|
|
|
config TIMER_GENERIC_REG
|
|
hex "Generic Timer Register Address"
|
|
default 0x004A2000 if TIMER_IPQ40XX
|
|
default 0x0200A028 if TIMER_IPQ806X
|
|
default 0x101C0100 if TIMER_MCT
|
|
default 0x10008068 if TIMER_MTK
|
|
default 0x100080A8 if TIMER_MTK_V2
|
|
default 0xff810028 if TIMER_RK3288
|
|
default 0xff850008 if TIMER_RK3399
|
|
default 0x60005010 if TIMER_TEGRA_1US
|
|
default 0x0
|
|
help
|
|
Register address to read generic time counter from.
|
|
|
|
config TIMER_GENERIC_HIGH_REG
|
|
hex "Generic Timer High Register Address"
|
|
default 0x004A2004 if TIMER_IPQ40XX
|
|
default 0x101C0104 if TIMER_MCT
|
|
default 0x10008078 if TIMER_MTK
|
|
default 0x100080B0 if TIMER_MTK_V2
|
|
default 0xff81002C if TIMER_RK3288
|
|
default 0xff85000C if TIMER_RK3399
|
|
default 0x0
|
|
help
|
|
Register address to read high 32 bits of generic time counter from.
|
|
Leave at 0x0 for 32-bit counters.
|