system76-coreboot

Files

Aaron Durbin 3674ccfa3e x86/mtrr: don't assume size of ROM cached during CAR mode

Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.

Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4846
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

2014-01-28 19:54:49 +01:00

arch

Multiboot: remove multiboot tables generation.

2014-01-23 20:37:48 +01:00

console

Remove sprintf

2014-01-10 18:08:31 +01:00

cpu

intel: fix microcode compilation failure in bootblock

2014-01-28 19:54:29 +01:00

device

lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content