373511b2f9
1201_ht_bus0_dev0_fidvid_mb.diff part 1 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
173 lines
4.5 KiB
C
173 lines
4.5 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "cpu/amd/dualcore/dualcore.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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/* Look up a which bus a given node/link combination is on.
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* return 0 when we can't find the answer.
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*/
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static unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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unsigned reg;
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for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
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unsigned config_map;
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config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
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if ((config_map & 3) != 3) {
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continue;
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}
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if ((((config_map >> 4) & 7) == node) &&
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(((config_map >> 8) & 3) == link))
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{
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return (config_map >> 16) & 0xff;
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}
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}
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return 0;
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}
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static void hard_reset(void)
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{
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device_t dev;
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/* Find the device */
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dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(dev, 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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device_t dev;
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/* Find the device */
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dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
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set_bios_reset();
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pci_write_config8(dev, 0x47, 1);
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}
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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}
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else {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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}
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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udelay(90);
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}
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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static void main(unsigned long bist)
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{
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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},
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#endif
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#if SECOND_CPU
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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},
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#endif
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};
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int needs_reset;
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if (bist == 0) {
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k8_init_and_stop_secondaries();
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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enable_smbus();
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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}
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