3855c01e0a
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pnp_type.h>
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#include <device/pnp.h>
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#include <stdint.h>
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#include "it8671f.h"
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/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
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#define SIO_BASE 0x3f0
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA (SIO_BASE + 1)
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/* Global configuration registers. */
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#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
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#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
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#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
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/*
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* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data.
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*/
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static const u8 init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
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0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
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};
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static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
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{
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outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
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outb(ldn, SIO_DATA);
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outb(index, SIO_BASE);
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outb(value, SIO_DATA);
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}
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/* Enter the configuration state (MB PnP mode). */
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static void it8671f_enter_conf(void)
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{
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int i;
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/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
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/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
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/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
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/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
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outb(0x86, IT8671F_CONFIGURATION_PORT);
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outb(0x80, IT8671F_CONFIGURATION_PORT);
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outb(0x55, IT8671F_CONFIGURATION_PORT);
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outb(0x55, IT8671F_CONFIGURATION_PORT);
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/* Sequentially write the 32 special values. */
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for (i = 0; i < 32; i++)
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outb(init_values[i], SIO_BASE);
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}
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/* Exit the configuration state (MB PnP mode). */
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static void it8671f_exit_conf(void)
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{
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
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}
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/* Select 48MHz CLKIN (24MHz is the default). */
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void it8671f_48mhz_clkin(void)
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{
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it8671f_enter_conf();
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
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it8671f_exit_conf();
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}
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/* Enable the serial port(s). */
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void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase)
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{
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it8671f_enter_conf();
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/*
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* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
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* PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
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*/
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
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/* Enable serial port(s). */
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it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
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it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
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it8671f_exit_conf();
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}
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