3855c01e0a
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include <device/pnp.h>
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#include <stdint.h>
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#include "lpc47m15x.h"
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static void pnp_enter_conf_state(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(0x55, port);
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}
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static void pnp_exit_conf_state(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(0xaa, port);
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}
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void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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