39264e2b3b
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
309 lines
8.5 KiB
C
309 lines
8.5 KiB
C
/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Initialisation of the PCI-to-ISA bridge and disabling the BIOS
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* write protection (for flash) in function 0 of the chip.
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* Enabling function 1 (IDE controller of the chip.
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*/
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/chip.h>
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#include <console/console.h>
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#include "w83c553f.h"
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#include "chip.h"
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#ifndef CONFIG_ISA_MEM
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#define CONFIG_ISA_MEM 0xFD000000
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#endif
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#ifndef CONFIG_ISA_IO
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#define CONFIG_ISA_IO 0xFE000000
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#endif
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#ifndef CONFIG_IDE_MAXBUS
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#define CONFIG_IDE_MAXBUS 2
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#endif
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#ifndef CONFIG_IDE_MAXDEVICE
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#define CONFIG_IDE_MAXDEVICE (CONFIG_IDE_MAXBUS*2)
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#endif
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uint32_t ide_bus_offset[CONFIG_IDE_MAXBUS];
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void initialise_pic(void);
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void initialise_dma(void);
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extern struct pci_ops pci_direct_ppc;
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#if 0
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void southbridge_early_init(void)
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{
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unsigned char reg8;
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/*
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* Set ISA memory space
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*/
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pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, ®8);
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/* 16 MB ISA memory space */
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, ®8);
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}
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#endif
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void w83c553_init(void)
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{
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struct device *dev;
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unsigned char reg8;
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unsigned short reg16;
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unsigned int reg32;
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dev = dev_find_device(W83C553F_VID, W83C553F_DID, 0);
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if (dev == 0)
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{
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printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
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return;
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}
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printk_info("Found W83C553F controller\n");
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/* always enabled */
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#if 0
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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#endif
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/*
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* Set ISA memory space
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*/
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reg8 = pci_read_config8(dev, W83C553F_IPADCR);
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/* 16 MB ISA memory space */
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reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
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reg8 &= ~W83C553F_IPADCR_MBE512;
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pci_write_config8(dev, W83C553F_IPADCR, reg8);
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/*
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* Chip select: switch off BIOS write protection
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*/
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reg8 = pci_read_config8(dev, W83C553F_CSCR);
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reg8 |= W83C553F_CSCR_UBIOSCSE;
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reg8 &= ~W83C553F_CSCR_BIOSWP;
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pci_write_config8(dev, W83C553F_CSCR, reg8);
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/*
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* Enable Port 92
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*/
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reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
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pci_write_config8(dev, W83C553F_CSCR, reg8);
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/*
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* Route IDE interrupts to IRQ 14 & 15 on 8259.
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*/
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pci_write_config8(dev, W83C553F_IDEIRCR, 0xef);
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pci_write_config16(dev, W83C553F_PCIIRCR, 0x0000);
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/*
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* Read IDE bus offsets from function 1 device.
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* We must unmask the LSB indicating that it is an IO address.
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*/
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dev = dev_find_device(W83C553F_VID, W83C553F_IDE, 0);
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if (dev == 0)
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{
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printk_info("Error: Cannot find W83C553F function 1 device\n");
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return;
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}
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/*
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* Enable native mode on IDE ports and set base address.
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*/
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reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
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pci_write_config8(dev, W83C553F_PIR, reg8);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0x1f0);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x3f6);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0x170);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0xffffffff);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
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pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0x376);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
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/*
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* Set read-ahead duration to 0xff
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* Enable P0 and P1
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*/
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reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
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pci_write_config32(dev, W83C553F_IDECSR, reg32);
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ide_bus_offset[0] = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
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ide_bus_offset[0] &= ~1;
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#if CONFIG_IDE_MAXBUS > 1
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ide_bus_offset[1] = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
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ide_bus_offset[1] &= ~1;
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#endif
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/*
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* Enable function 1, IDE -> busmastering and IO space access
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*/
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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/*
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* Initialise ISA interrupt controller
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*/
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initialise_pic();
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/*
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* Initialise DMA controller
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*/
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initialise_dma();
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printk_info("W83C553F configuration complete\n");
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}
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void initialise_pic(void)
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{
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outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
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outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
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outb(W83C553F_PIC1_ELC, 0xf8); /* all IRQ's edge sensitive */
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outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
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outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
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outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
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outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
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outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
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outb(W83C553F_PIC2_ELC, 0xde); /* all IRQ's edge sensitive */
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outb(W83C553F_TMR1_CMOD, 0x74);
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outb(W83C553F_PIC2_OCW1, 0x20);
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outb(W83C553F_PIC1_OCW1, 0x20);
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outb(W83C553F_PIC2_OCW1, 0x2b);
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outb(W83C553F_PIC1_OCW1, 0x2b);
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}
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void initialise_dma(void)
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{
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unsigned int channel;
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unsigned int rvalue1, rvalue2;
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/* perform a H/W reset of the devices */
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outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
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/* initialise all channels to a sane state */
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for (channel = 0; channel < 4; channel++) {
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/*
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* dependent upon the channel, setup the specifics:
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*
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* demand
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* address-increment
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* autoinitialize-disable
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* verify-transfer
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*/
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switch (channel) {
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case 0:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
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break;
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case 1:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
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break;
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case 2:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
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break;
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case 3:
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
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break;
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default:
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rvalue1 = 0x00;
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rvalue2 = 0x00;
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break;
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}
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/* write to write mode registers */
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outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
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outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
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}
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/* enable all channels */
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outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
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/*
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* initialize the global DMA configuration
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*
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* DACK# active low
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* DREQ active high
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* fixed priority
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* channel group enable
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*/
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outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
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outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
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}
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void southbridge_init(struct chip *chip, enum chip_pass pass)
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{
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struct southbridge_winbond_w83c553_config *conf = (struct southbridge_winbond_w83c553_config *)chip->chip_info;
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switch (pass) {
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case CONF_PASS_POST_PCI:
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w83c553_init();
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break;
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default:
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/* nothing yet */
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break;
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}
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}
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struct chip_control southbridge_winbond_w83c553_control = {
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enable: southbridge_init,
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name: "Winbond W83C553"
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};
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