3a14338625
This patch includes support for both ICL ES0 and ES1 samples. Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md TEST=Able to build and boot dragonegg. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
84 lines
1.5 KiB
Plaintext
84 lines
1.5 KiB
Plaintext
config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_SPI_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_ICELAKE
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if BOARD_GOOGLE_BASEBOARD_DRAGONEGG
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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# Select this option to enable use of cr50 SPI TPM on dragon egg.
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config DRAGONEGG_USE_SPI_TPM
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bool
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default y
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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config DRIVER_TPM_SPI_BUS
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depends on DRAGONEGG_USE_SPI_TPM
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default 0x1
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config GBB_HWID
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string
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depends on CHROMEOS
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default "DRAGONEGG TEST 1394"
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config MAINBOARD_DIR
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string
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default "google/dragonegg"
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config MAINBOARD_PART_NUMBER
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string
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default "Dragonegg"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config MAINBOARD_FAMILY
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string
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default "Google_Dragonegg"
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config MAX_CPUS
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int
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default 8
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 48 # GPE0_DW1_16 (GPP_D16)
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config VARIANT_DIR
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string
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default "dragonegg" if BOARD_GOOGLE_DRAGONEGG
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config UART_FOR_CONSOLE
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int
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default 0
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config VBOOT
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select VBOOT_LID_SWITCH
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG
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