3a75e5e864
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
130 lines
4.6 KiB
C
130 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This code was originally generated using an i915tool program. It has been
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* improved by hand.
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*/
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#include <stdint.h>
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#include <console/console.h>
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#include <delay.h>
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#include <drivers/intel/gma/i915.h>
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#include <arch/io.h>
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#include "mainboard.h"
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/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
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void runio(struct intel_dp *dp);
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void runio(struct intel_dp *dp)
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{
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u8 read_val;
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intel_dp_wait_panel_power_control(0xabcd0008);
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/* vbios spins at this point. Some haswell weirdness? */
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intel_dp_wait_panel_power_control(0xabcd0008);
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/* This should be a function like intel_panel_enable_backlight
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However, we are not sure how the value 0x3a9 comes up.
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It has to do something with PWM frequency */
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gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
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gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
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gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
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gtt_write(DEIIR,0x00008000);
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intel_dp_wait_reg(DEIIR, 0x00000000);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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intel_dp_sink_dpms(dp, 0);
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intel_dp_get_max_downspread(dp, &read_val);
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intel_dp_set_m_n_regs(dp);
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intel_dp_set_resolution(dp);
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gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
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gtt_write(PIPECONF(dp->transcoder),0x00000000);
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gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
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mainboard_set_port_clk_dp(dp);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
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gtt_write(DEIIR,0x00000080);
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gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
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gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
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intel_dp_wait_panel_power_control(0xabcd000a);
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/* what is this doing? Not sure yet. */
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intel_dp_i2c_write(dp, 0x0);
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intel_dp_i2c_read(dp, &read_val);
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intel_dp_i2c_write(dp, 0x04);
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intel_dp_i2c_read(dp, &read_val);
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intel_dp_i2c_write(dp, 0x7e);
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intel_dp_i2c_read(dp, &read_val);
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/* this needs to be a call to a function */
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gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
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gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
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gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
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/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
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gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
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gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
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intel_dp_set_bw(dp);
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intel_dp_set_lane_count(dp);
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mainboard_train_link(dp);
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/* need a function: intel_ddi_set_tp or similar */
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gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
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gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
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gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
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gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
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gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
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/* some of this is not needed. */
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gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
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gtt_write(SDEIIR,0x00000000);
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gtt_write(DEIIR,0x00000000);
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gtt_write(DEIIR,0x00008000);
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intel_dp_wait_reg(DEIIR, 0x00000000);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
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gtt_write(DEIIR,0x00000080);
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intel_dp_wait_reg(DEIIR, 0x00000000);
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gtt_write(DSPSTRIDE(dp->plane),dp->stride);
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gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
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gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
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gtt_write(SDEIIR,0x00000000);
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gtt_write(SDEIIR,0x00000000);
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gtt_write(DEIIR,0x00000000);
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}
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