3a988ccebf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifdfdbf193bd96a6dda72a2f23d51925fd369aa01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Phoenix */
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/* TODO: See what can be made common */
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/* ACPI - create the Fixed ACPI Description Tables (FADT) */
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/cppc.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/ioapic.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <console/console.h>
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#include <cpu/amd/cpuid.h>
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#include <device/device.h>
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#include <soc/iomap.h>
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#include <types.h>
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#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
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#include "chip.h"
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/*
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* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
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* in the ACPI 3.0b specification.
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*/
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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const struct soc_amd_phoenix_config *cfg = config_of_soc();
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if (CONFIG(PLATFORM_USES_FSP2_0)) {
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
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fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
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fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
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fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
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fadt->gpe0_blk = ACPI_GPE0_BLK;
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} else {
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/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
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opensil_fill_fadt_io_ports(fadt);
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}
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fadt->pm1_evt_len = 4; /* 32 bits */
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fadt->pm1_cnt_len = 2; /* 16 bits */
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fadt->pm_tmr_len = 4; /* 32 bits */
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fadt->gpe0_blk_len = 8; /* 64 bits */
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fill_fadt_extended_pm_io(fadt);
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fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */
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fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_PLATFORM_CLOCK |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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if (cfg->s0ix_enable)
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fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
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fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
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}
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unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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/* IVRS */
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current = acpi_add_ivrs_table(current, rsdp);
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if (CONFIG(PLATFORM_USES_FSP2_0))
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current = acpi_add_fsp_tables(current, rsdp);
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else
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current = acpi_add_opensil_tables(current, rsdp);
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return current;
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}
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const acpi_cstate_t cstate_cfg_table[] = {
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[0] = {
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.ctype = 1,
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.latency = 1,
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.power = 0,
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},
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[1] = {
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.ctype = 2,
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.latency = 0x12,
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.power = 0,
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},
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[2] = {
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.ctype = 3,
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.latency = 350,
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.power = 0,
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},
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};
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const acpi_cstate_t *get_cstate_config_data(size_t *size)
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{
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*size = ARRAY_SIZE(cstate_cfg_table);
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return cstate_cfg_table;
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}
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