3b5b9f4c54
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib6edae61fb904143c3b3994df812524a258fa9f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
114 lines
3.2 KiB
Plaintext
114 lines
3.2 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */
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}"
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register "eist_enable" = "1"
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device cpu_cluster 0 on end
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device domain 0 on
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subsystemid 0x103c 0x2b5e inherit
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device ref peg0 on end
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device ref igpu on end
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device ref sa_thermal on end
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device ref gmm on end
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device ref south_xhci on
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register "usb2_ports" = "{
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[0] = USB2_PORT_MID(OC0),
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[1] = USB2_PORT_MID(OC0),
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[2] = USB2_PORT_MID(OC4),
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[3] = USB2_PORT_MID(OC4),
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[4] = USB2_PORT_MID(OC2),
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[5] = USB2_PORT_MID(OC2),
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[6] = USB2_PORT_MID(OC0),
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[7] = USB2_PORT_MID(OC0),
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[8] = USB2_PORT_MID(OC0),
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[9] = USB2_PORT_MID(OC0),
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[10] = USB2_PORT_MID(OC1),
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[11] = USB2_PORT_MID(OC1),
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[12] = USB2_PORT_MID(OC_SKIP),
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[13] = USB2_PORT_MID(OC_SKIP),
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}"
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register "usb3_ports" = "{
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[0] = USB3_PORT_DEFAULT(OC0),
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[1] = USB3_PORT_DEFAULT(OC0),
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[2] = USB3_PORT_DEFAULT(OC3),
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[3] = USB3_PORT_DEFAULT(OC3),
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[4] = USB3_PORT_DEFAULT(OC1),
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[5] = USB3_PORT_DEFAULT(OC1),
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[6] = USB3_PORT_DEFAULT(OC_SKIP),
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[7] = USB3_PORT_DEFAULT(OC_SKIP),
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[8] = USB3_PORT_DEFAULT(OC_SKIP),
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[9] = USB3_PORT_DEFAULT(OC_SKIP),
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}"
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end
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device ref thermal on end
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device ref heci1 on end
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device ref sata on
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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register "SataPortsHotPlug" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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# DevSlp not supported
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end
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device ref uart2 on end
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device ref pcie_rp5 on
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpClkSrcNumber[4]" = "11"
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end
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device ref pcie_rp6 on
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register "PcieRpEnable[5]" = "1"
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register "PcieRpHotPlug[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpClkSrcNumber[5]" = "6"
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end
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device ref pcie_rp7 on
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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register "PcieRpClkSrcNumber[6]" = "10"
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end
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device ref pcie_rp8 on
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register "PcieRpEnable[7]" = "1"
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register "PcieRpHotPlug[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieRpAdvancedErrorReporting[7]" = "1"
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register "PcieRpClkSrcNumber[7]" = "12"
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end
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device ref lpc_espi on
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# FIXME: Missing Super I/O HWM config
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register "gen1_dec" = "0x000c0291"
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end
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device ref pmc on
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register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
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register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
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register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
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register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
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register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
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end
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device ref hda on end
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device ref smbus on end
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device ref fast_spi on end
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device ref tracehub on
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register "TraceHubMemReg0Size" = "2"
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register "TraceHubMemReg1Size" = "2"
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end
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end
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end
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