3b618bbe31
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
208 lines
6.0 KiB
C
208 lines
6.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <version.h>
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#include "../qemu-i440fx/fw_cfg.h"
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#include "../qemu-i440fx/acpi.h"
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#include <southbridge/intel/i82801ix/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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/* Enable both COM ports */
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gnvs->cmap = 0x01;
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gnvs->cmbp = 0x01;
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/* IGD Displays */
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gnvs->ndid = 0; /* Will use default of 0x00000400. */
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}
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void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
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memset((void *) fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = sizeof(acpi_fadt_t);
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header->revision = get_acpi_table_revision(FADT);
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memcpy(header->oem_id, OEM_ID, 6);
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memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
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memcpy(header->asl_compiler_id, ASLC, 4);
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header->asl_compiler_revision = asl_revision;
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fadt->firmware_ctrl = (unsigned long) facs;
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fadt->dsdt = (unsigned long) dsdt;
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fadt->reserved = 0x00;
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fadt->preferred_pm_profile = PM_MOBILE;
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fadt->sci_int = 0x9;
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fadt->smi_cmd = 0;
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fadt->acpi_enable = 0;
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fadt->acpi_disable = 0;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = pmbase;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + 0x4;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + 0x50;
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fadt->pm_tmr_blk = pmbase + 0x8;
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fadt->gpe0_blk = pmbase + 0x20;
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fadt->gpe1_blk = 0;
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2; /* Upper word is reserved and
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Linux complains about 32 bit. */
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0;
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = 0x39;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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fadt->duty_width = 3;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x32;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
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fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
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ACPI_FADT_PLATFORM_CLOCK;
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = 0;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = 0x06;
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fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */
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fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */
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/* then FIRMWARE_CTRL must be zero. */
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fadt->x_dsdt_l = (unsigned long)dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = 0;
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fadt->x_pm1a_evt_blk.addrl = pmbase;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 0;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and
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Linux complains about 32 bit. */
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = 0;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 0;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = 0;
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fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = 0;
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fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 128;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = 0;
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fadt->x_gpe0_blk.addrl = pmbase + 0x20;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 0;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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header->checksum = acpi_checksum((void *) fadt, header->length);
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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struct device *dev;
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u32 reg;
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dev = dev_find_device(0x8086, 0x29c0, 0);
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if (!dev)
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return current;
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reg = pci_read_config32(dev, 0x60);
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if ((reg & 0x07) != 0x01) /* require enabled + 256MB size */
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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reg & 0xf0000000, 0x0, 0x0, 255);
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return current;
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}
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