3c838c7399
PCI resources MMIO space/bus master enabling is handled inside pch_dev_enable_resources() from common device code. Hence no need to have an explicit soc function to do the same. TEST=lspci from kernel console shows same pci device list without and without this patch. Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
33 lines
912 B
C
33 lines
912 B
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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u8 pch_revision(void)
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{
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return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);
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}
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u16 pch_type(void)
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{
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return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
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}
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