3cfb6a066b
Add a clock control driver to initialize the clock tree inside the
low-power audio subsystem. Depthcharge builds up on this to enable
audio function on storm.
The clock is hardcoded for 48KHz frame rate, two 16 bit channels.
BRANCH=storm
BUG=chrome-os-partner:35247
TEST=with depthcharge patches applied and Using depthcharge CLI audio
test program verified that the target generates sensible sounds
audio 100 100
audio 1000 5000
Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760
Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f
Original-Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248830
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/9758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
91 lines
2.8 KiB
Makefile
91 lines
2.8 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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bootblock-y += clock.c
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bootblock-y += gpio.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-y += timer.c
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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verstage-y += clock.c
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verstage-y += gpio.c
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verstage-y += gsbi.c
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verstage-y += i2c.c
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verstage-y += qup.c
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verstage-y += spi.c
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verstage-y += timer.c
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verstage-$(CONFIG_CONSOLE_SERIAL_IPQ806X) += uart.c
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romstage-y += clock.c
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romstage-y += blobs_init.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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romstage-y += timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-y += cbmem.c
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ramstage-y += blobs_init.c
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ramstage-y += cbmem.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += lcc.c
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ramstage-y += soc.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-y += timer.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += usb.c
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ramstage-y += tz_wrapper.S
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ifeq ($(CONFIG_USE_BLOBS),y)
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# Generate the actual coreboot bootblock code
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$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_bootblock) -O binary $< $@.tmp
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@mv $@.tmp $@
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# Add MBN header to allow SBL3 to start coreboot bootblock
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$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
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@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
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./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
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@mv $@.tmp $@
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# Create a complete bootblock which will start up the system
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$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
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$(objcbfs)/bootblock.mbn
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@printf " MBNCAT $(subst $(obj)/,,$(@))\n"
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@util/ipqheader/mbncat.py -o $@.tmp $^
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@mv $@.tmp $@
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endif
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CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
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# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
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mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
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# Location of the binary blobs
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mbn-root := 3rdparty/cpu/qualcomm/ipq806x
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# Create make variables to aid cbfs-files-handler in processing the blobs (add
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# them all as raw binaries at the root level).
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$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\
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$(eval $(f)-file := $(mbn-root)/$(f))\
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$(eval $(f)-type := raw))
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