3d15e10aef
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
114 lines
2.7 KiB
Plaintext
114 lines
2.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOC_INTEL_FSP_BAYTRAIL
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bool
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help
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Bay Trail I part support using the Intel FSP.
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if SOC_INTEL_FSP_BAYTRAIL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select HAVE_SMI_HANDLER
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select HAVE_HARD_RESET
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select RELOCATABLE_MODULES
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select PARALLEL_MP
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select REG_SCRIPT
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select TSC_CONSTANT_RATE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select SUPPORT_CPU_UCODE_IN_CBFS
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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# Microcode header files are delivered in FSP package
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select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
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config SOC_INTEL_FSP_BAYTRAIL_MD
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bool
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default n
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/fsp_baytrail/bootblock/bootblock.c"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config MAX_CPUS
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int
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default 4
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config CPU_ADDR_BITS
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int
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default 36
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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help
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This is set by the FSP
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config VGA_BIOS_ID
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string
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default "8086,0f31"
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help
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This is the default PCI ID for the Bay Trail graphics
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devices. This string names the vbios ROM in cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable built-in legacy Serial Port"
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help
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The Baytrail SOC has one legacy serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config VGA_BIOS_FILE
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string
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default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
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config FSP_BAYTRAIL_GFX_INIT
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default n
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bool
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help
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Enabling this option will activate graphics init code. With this init,
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the graphic power gate registers will be initialized before
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VBIOS is executed.
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config CPU_MICROCODE_HEADER_FILES
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string
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default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
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## Baytrail Specific FSP Kconfig
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source src/soc/intel/fsp_baytrail/fsp/Kconfig
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endif #SOC_INTEL_FSP_BAYTRAIL
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