Files
system76-coreboot/src
Angel Pons 3d3bf484f5 nb/intel/sandybridge: Introduce ddr3_mirror_mrreg helper
Write training needs to update mode register 1, but `write_mrreg` will
clobber the IOSAV sequence. Reference code uses one four-subsequence to
unset Qoff in MR1, run the test, and finally set Qoff again. This will
be implemented in future changes, and will use the newly-added helper.

Change-Id: I06a06a7bdd43dbde34af4ea2f90e00873eefe599
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 00:34:17 +00:00
..
2020-11-19 22:58:11 +00:00
2020-11-19 14:48:31 +00:00
2020-11-19 14:48:31 +00:00