3d966255a4
BUG=b:35647967 TEST=boot from bob Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820 Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452286 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19434 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
138 lines
3.9 KiB
C
138 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/grf.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/i2c.h>
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#include <soc/pwm.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "board.h"
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#include "pwm_regulator.h"
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void bootblock_mainboard_early_init(void)
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{
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/* Let gpio2ab io domains works at 1.8V.
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*
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* If io_vsel[0] == 0(default value), gpio2ab io domains is 3.0V
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* powerd by APIO2_VDD, otherwise, 1.8V supplied by APIO2_VDDPST.
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* But from the schematic of kevin rev0, the APIO2_VDD and
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* APIO2_VDDPST both are 1.8V(intentionally?).
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*
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* So, by default, CPU1_SDIO_PWREN(GPIO2_A2) can't output 3.0V
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* because the supply is 1.8V.
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* Let ask GPIO2_A2 output 1.8V to make GPIO interal logic happy.
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*/
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write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 0));
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/*
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* Let's enable these power rails here, we are already running the SPI
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* Flash based code.
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*/
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gpio_output(GPIO(0, B, 2), 1); /* PP1500_EN */
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gpio_output(GPIO(0, B, 4), 1); /* PP3000_EN */
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#if IS_ENABLED(CONFIG_DRIVERS_UART)
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_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
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"CONSOLE_SERIAL_UART should be UART2");
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/* iomux: select gpio4c[4:3] as uart2 dbg port */
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write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
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/* grf soc_con7[11:10] use for uart2 select */
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write32(&rk3399_grf->soc_con7, UART2C_SEL);
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#endif
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}
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static void configure_spi_flash(void)
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{
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gpio_input(GPIO(1, A, 7)); /* SPI1_MISO remove pull-up */
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gpio_input(GPIO(1, B, 0)); /* SPI1_MOSI remove pull-up */
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gpio_input(GPIO(1, B, 1)); /* SPI1_CLK remove pull-up */
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gpio_input(GPIO(1, B, 2)); /* SPI1_CS remove pull-up */
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rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33*MHz);
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rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);
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write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
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write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
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}
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static void configure_ec(void)
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{
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gpio_input(GPIO(2, C, 4)); /* SPI5_MISO remove pull-up */
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gpio_input(GPIO(2, C, 5)); /* SPI5_MOSI remove pull-up */
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gpio_input(GPIO(2, C, 6)); /* SPI5_CLK remove pull-up */
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gpio_input_pullup(GPIO(2, C, 7)); /* SPI5_CS confirm pull-up */
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750);
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write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);
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}
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static void configure_tpm(void)
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{
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if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) {
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gpio_input(GPIO(3, A, 4)); /* SPI0_MISO remove pull-up */
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gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI remove pull-up */
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gpio_input(GPIO(3, A, 6)); /* SPI0_CLK remove pull-up */
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gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS confirm */
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rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
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write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
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gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING);
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} else {
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gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */
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gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */
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i2c_init(0, 400*KHz);
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write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
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write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
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}
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}
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static void speed_up_boot_cpu(void)
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{
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pwm_regulator_configure(PWM_REGULATOR_LIT, 1150);
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udelay(200);
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rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE);
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}
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void bootblock_mainboard_init(void)
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{
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speed_up_boot_cpu();
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if (rkclk_was_watchdog_reset())
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reboot_from_watchdog();
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configure_spi_flash();
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configure_ec();
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configure_tpm();
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setup_chromeos_gpios();
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}
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