3df6cc9de6
For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
34 lines
893 B
Makefile
34 lines
893 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
|
|
|
|
ramstage-y += acpi.c
|
|
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y)
|
|
ramstage-y += acpi_apic.c
|
|
ramstage-y += acpi_dmar.c
|
|
ramstage-y += acpi_hpet.c
|
|
endif
|
|
ramstage-y += acpigen.c
|
|
ramstage-y += acpigen_dptf.c
|
|
ramstage-y += acpigen_dsm.c
|
|
ramstage-$(CONFIG_PCI) += acpigen_pci.c
|
|
ramstage-y += acpigen_ps2_keybd.c
|
|
ramstage-y += acpigen_usb.c
|
|
ramstage-y += device.c
|
|
ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c
|
|
ramstage-y += pld.c
|
|
ramstage-y += sata.c
|
|
ramstage-y += soundwire.c
|
|
ramstage-y += fadt_filler.c
|
|
ramstage-$(CONFIG_ACPI_COMMON_MADT_GICC_V3) += acpi_gic.c
|
|
|
|
all-y += acpi_pm.c
|
|
smm-y += acpi_pm.c
|
|
|
|
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),)
|
|
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
|
|
endif
|
|
$(eval $(call asl_template,dsdt))
|
|
|
|
endif # CONFIG_HAVE_ACPI_TABLES
|