6e079dc120
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
27 lines
720 B
Makefile
27 lines
720 B
Makefile
ramstage-y += haswell_init.c
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romstage-y += romstage.c
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romstage-y += ../car/romstage.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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smm-y += finalize.c
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bootblock-y += ../car/non-evict/cache_as_ram.S
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bootblock-y += ../car/bootblock.c
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bootblock-y += ../../x86/early_reset.S
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bootblock-y += bootblock.c
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postcar-y += ../car/non-evict/exit_car.S
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../turbo
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*)
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*)
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