3eab7ed45e
This change shows the source structure for nvidia Tegra and Tegra124 SOC. The problem we are trying to solve is that there is a large amount of common code in the form of .c and .h files across many different Tegra SOCs. The solution is to provide common code in a single directory, but not to compile in the common code directory; rather, we compile in a directory for a given SOC. Different SOCs will sometimes need different bits of code from the common directory. Tegra common code lives in tegra/, but there is no makefile there: if a Tegra common file is needed in a SOC, it is referenced via a Makefile in a specific Tegra SOC. Another issue is includes. Include files in the common directory might be accessed by a piece of code in an SOC directory. More problematically, code in the common directory might require a file in an SOC directory. We don't want to put the SOC name in an #include path, e.g. in a C file in tegra/ is very undesirable, since we might be compiling for a tegra114. On some systems this is solved by a pre-pass which creates a set of symbolic links; on others with nested #ifdef in the common code which include different .h files depending on CPP variables. In previous years, both LinuxBIOS and coreboot have tried these solutions and found them inconvenient and error-prone. We choose to solve it by requiring explicit naming of part of the path of files that are in the common directory. This requirement, coupled with two -I directives in the Makefile.inc, allows common and SOC C code to incorporate both common and SOC .h files. .c and .h files -- SOC or common -- name include files in the common directory with the prefix tegra/, e.g. SOC files will be included from the SOC directory if they have no prefix: The full patch of clock.h will depend on what SOC is being compiled, which is desirable. In this way, a common file can pick up a specific SOC file without creating symlinks or other such tricky magic. We show this usage with one file, soc/nvidia/tega124/clock.c. This compiles. The last question is where to put the prototype for the function defined in this file -- soc.h? Change-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/171569 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 53e3bed868953f3da588ec90661d316a6482e27e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6621 Tested-by: build bot (Jenkins)
65 lines
2.6 KiB
C
65 lines
2.6 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright 2013 Google Inc.
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*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA124_SOC_H
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/* AP base physical address of internal SRAM */
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#define NV_PA_BASE_SRAM 0x40000000
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#define NV_PA_BASE_SRAM_SIZE 0x20000
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/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
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#define NV_WB_RUN_ADDRESS 0x40020000
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#define NV_PA_ARM_PERIPHBASE 0x50040000
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#define NV_PA_PG_UP_BASE 0x60000000
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#define NV_PA_TMRUS_BASE 0x60005010
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#define NV_PA_CLK_RST_BASE 0x60006000
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#define NV_PA_FLOW_BASE 0x60007000
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#define NV_PA_GPIO_BASE 0x6000D000
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#define NV_PA_EVP_BASE 0x6000F000
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#define NV_PA_APB_MISC_BASE 0x70000000
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#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
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#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
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#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
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#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
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#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
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#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
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#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
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#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
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#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
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#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
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#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
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#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
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#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
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#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
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#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
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#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
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#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
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#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
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#define NV_PA_CSITE_BASE 0x70040000
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#define TEGRA_USB_ADDR_MASK 0xFFFFC000
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#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
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#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
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#endif /* _TEGRA124_SOC_H_ */
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