3eb8dbaee2
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
142 lines
4.6 KiB
C
142 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Based on src/southbridge/via/vt8237r/vt8237_fadt.c
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*/
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#include <acpi/acpi.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <version.h>
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#include "i82371eb.h"
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/**
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* Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
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* Reference: ACPIspec40a, 5.2.9, page 118
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*/
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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fadt->sci_int = 9;
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if (permanent_smi_handler()) {
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/* TODO: SMI handler is not implemented. */
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fadt->smi_cmd = 0x00;
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}
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fadt->pm1a_evt_blk = DEFAULT_PMBASE;
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fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL;
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fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR;
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fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS;
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/* *_len define register width in bytes */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 4;
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fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
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fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
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fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
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fadt->duty_width = 3; /* this width is in bits */
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fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
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fadt->mon_alrm = 0x0; /* not supported */
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fadt->century = 0x0; /* not supported */
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/*
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* bit meaning
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* 0 1: We have user-visible legacy devices
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* 1 1: 8042
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* 2 0: VGA is ok to probe
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* 3 1: MSI are not supported
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*/
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fadt->iapc_boot_arch = 0xb;
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/*
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* bit meaning
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* 0 WBINVD
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* Processors in new ACPI-compatible systems are required to
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* support this function and indicate this to OSPM by setting
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* this field.
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* 1 WBINVD_FLUSH
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* If set, indicates that the hardware flushes all caches on the
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* WBINVD instruction and maintains memory coherency, but does
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* not guarantee the caches are invalidated.
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* 2 PROC_C1
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* C1 power state (x86 hlt instruction) is supported on all cpus
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* 3 P_LVL2_UP
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* 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor
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* 4 PWR_BUTTON
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* 0: pwr button is fixed feature
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* 1: pwr button has control method device if present
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* 5 SLP_BUTTON
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* 0: sleep button is fixed feature
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* 1: sleep button has control method device if present
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* 6 FIX_RTC
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* 0: RTC wake status supported in fixed register spce
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* 7 RTC_S4
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* 1: RTC can wake from S4
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* 8 TMR_VAL_EXT
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* 1: pmtimer is 32bit, 0: pmtimer is 24bit
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* 9 DCK_CAP
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* 1: system supports docking station
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* 10 RESET_REG_SUPPORT
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* 1: fadt describes reset register for system reset
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* 11 SEALED_CASE
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* 1: No expansion possible, sealed case
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* 12 HEADLESS
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* 1: Video output, keyboard and mouse are not connected
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* 13 CPU_SW_SLP
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* 1: Special processor instruction needs to be executed
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* after writing SLP_TYP
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* 14 PCI_EXP_WAK
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* 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set
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* on platforms with pci express support
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* 15 USE_PLATFORM_CLOCK
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* 1: OS should prefer platform clock over processor internal
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* clock.
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* 16 S4_RTC_STS_VALID
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* 17 REMOTE_POWER_ON_CAPABLE
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* 1: platform correctly supports OSPM leaving GPE wake events
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* armed prior to an S5 transition.
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* 18 FORCE_APIC_CLUSTER_MODEL
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* 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE
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*/
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fadt->flags |= 0xa5 | ACPI_FADT_RESET_REGISTER;
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0;
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fadt->reset_value = 0x06;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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}
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