400ce55566
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation..
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* Copyright (C) 2017 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/amdfam15.h>
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#include <smp/node.h>
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#include <bootblock_common.h>
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include <timestamp.h>
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#include <halt.h>
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#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB"
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#endif
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#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000
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#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB"
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#endif
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/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
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static void amd_initmmio(void)
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{
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msr_t mmconf;
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msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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int mtrr;
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mmconf.hi = 0;
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mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
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| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
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wrmsr(MMIO_CONF_BASE, mmconf);
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/*
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* todo: AGESA currently writes variable MTRRs. Once that is
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* corrected, un-hardcode this MTRR.
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*
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* Be careful not to use get_free_var_mtrr/set_var_mtrr pairs
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* where all cores execute the path. Both cores within a compute
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* unit share MTRRs. Programming core0 has the appearance of
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* modifying core1 too. Using the pair again will create
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* duplicate copies.
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*/
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;
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set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK);
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mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM;
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set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE,
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CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE);
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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amd_initmmio();
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/*
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* Call lib/bootblock.c main with BSP, shortcut for APs
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*/
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if (!boot_cpu()) {
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void (*ap_romstage_entry)(void) =
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(void (*)(void))get_ap_entry_ptr();
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ap_romstage_entry(); /* execution does not return */
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halt();
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}
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/* TSC cannot be relied upon. Override the TSC value passed in. */
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bootblock_main_with_timestamp(timestamp_get(), NULL, 0);
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}
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void bootblock_soc_early_init(void)
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{
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/*
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* This call (sb_reset_i2c_slaves) was originally early at
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* bootblock_c_entry, but had to be moved here. There was an
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* unexplained delay in the middle of the i2c transaction when
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* we had it in bootblock_c_entry. Moving it to this point
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* (or adding delays) fixes the issue. It seems like the processor
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* just pauses but we don't know why.
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*/
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sb_reset_i2c_slaves();
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bootblock_fch_early_init();
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post_code(0x90);
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}
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void bootblock_soc_init(void)
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{
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if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
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assert(CONFIG_UART_FOR_CONSOLE >= 0
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&& CONFIG_UART_FOR_CONSOLE <= 1);
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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bootblock_fch_init();
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/* Initialize any early i2c buses. */
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i2c_soc_early_init();
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}
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