401ec98e06
Change-Id: I4ad080653c9af94a4dc73d93ddc4c8c117a682b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <stdint.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <pc80/isa-dma.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/ioapic.h>
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#if CONFIG(HAVE_ACPI_TABLES)
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#endif
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#include "i82371eb.h"
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#include "chip.h"
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static void isa_init(struct device *dev)
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{
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u32 reg32;
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struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
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/* Initialize the real time clock (RTC). */
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cmos_init(0);
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/*
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* Enable special cycles, needed for soft poweroff.
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*/
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);
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/*
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* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
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* bus, which is a subset of ISA. We select the full ISA bus here.
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*/
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reg32 = pci_read_config32(dev, GENCFG);
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reg32 |= ISA; /* Select ISA, not EIO. */
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/* Some boards use GPO22/23. Select it if configured. */
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reg32 = ONOFF(sb->gpo22_enable, reg32, GPO2223);
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pci_write_config32(dev, GENCFG, reg32);
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/* Initialize ISA DMA. */
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isa_dma_init();
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/*
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* Unlike most other southbridges the 82371EB doesn't have a built-in
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* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
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* have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
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*
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* Thus, we can/must only enable the IOAPIC if it actually exists,
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* i.e. the respective mainboard does "select IOAPIC".
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*/
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if (CONFIG(IOAPIC)) {
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u16 reg16;
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u8 ioapic_id = 2;
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/* Enable IOAPIC. */
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reg16 = pci_read_config16(dev, XBCS);
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reg16 |= (1 << 8); /* APIC Chip Select */
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pci_write_config16(dev, XBCS, reg16);
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/* Set and verify the IOAPIC ID. */
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set_ioapic_id(VIO_APIC_VADDR, ioapic_id);
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if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR))
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die("IOAPIC error!\n");
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}
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}
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static void sb_read_resources(struct device *dev)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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res = new_resource(dev, 1);
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res->base = 0x0UL;
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res->size = 0x1000UL;
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 2);
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res->base = 0xff800000UL;
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res->size = 0x00800000UL; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
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IORESOURCE_RESERVE;
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#if CONFIG(IOAPIC)
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
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IORESOURCE_RESERVE;
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#endif
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}
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static const struct device_operations isa_ops = {
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.read_resources = sb_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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#if CONFIG(HAVE_ACPI_TABLES)
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.write_acpi_tables = acpi_write_hpet,
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.acpi_fill_ssdt = generate_cpu_entries,
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#endif
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.init = isa_init,
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.scan_bus = scan_static_bus,
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.ops_pci = 0, /* No subsystem IDs on 82371EB! */
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};
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static const struct pci_driver isa_driver __pci_driver = {
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.ops = &isa_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
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};
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static const struct pci_driver isa_SB_driver __pci_driver = {
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.ops = &isa_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371SB_ISA,
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};
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