baf27dbaeb
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
127 lines
4.3 KiB
Plaintext
127 lines
4.3 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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/* CACHE_ROM_SIZE defined here. */
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#include <cpu/x86/mtrr.h>
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/* This file is included inside a SECTIONS block */
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. = CONFIG_DCACHE_RAM_BASE;
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.car.data . (NOLOAD) : {
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_car_region_start = . ;
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#if CONFIG(PAGING_IN_CACHE_AS_RAM)
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/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
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* aligned when using this option. */
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_pagetables = . ;
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. += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
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_epagetables = . ;
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#endif
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#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
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/* Vboot work buffer only needs to be available when verified boot
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* starts in bootblock. */
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VBOOT2_WORK(., 12K)
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#endif
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#if CONFIG(TPM_MEASURED_BOOT)
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/* Vboot measured boot TCPA log measurements.
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* Needs to be transferred until CBMEM is available */
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TPM_TCPA_LOG(., 2K)
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#endif
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/* Stack for CAR stages. Since it persists across all stages that
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* use CAR it can be reused. The chipset/SoC is expected to provide
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* the stack size. */
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_car_stack = .;
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. += CONFIG_DCACHE_BSP_STACK_SIZE;
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_ecar_stack = .;
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/* The pre-ram cbmem console as well as the timestamp region are fixed
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* in size. Therefore place them above the car global section so that
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* multiple stages (romstage and verstage) have a consistent
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* link address of these shared objects. */
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PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
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#if CONFIG(PAGING_IN_CACHE_AS_RAM)
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. = ALIGN(32);
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/* Page directory pointer table resides here. There are 4 8-byte entries
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* totalling 32 bytes that need to be 32-byte aligned. The reason the
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* pdpt are not colocated with the rest of the page tables is to reduce
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* fragmentation of the CAR space that persists across stages. */
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_pdpt = .;
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. += 32;
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_epdpt = .;
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#endif
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TIMESTAMP(., 0x200)
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#if !CONFIG(NO_CBFS_MCACHE)
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CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
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#endif
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#if !CONFIG(NO_FMAP_CACHE)
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FMAP_CACHE(., FMAP_SIZE)
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#endif
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_car_ehci_dbg_info = .;
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/* Reserve sizeof(struct ehci_dbg_info). */
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. += 80;
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_ecar_ehci_dbg_info = .;
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/* _bss and _ebss provide symbols to per-stage
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* variables that are not shared like the timestamp and the pre-ram
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* cbmem console. This is useful for clearing this area on a per-stage
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* basis when more than one stage uses cache-as-ram. */
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_bss = .;
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/* Allow global uninitialized variables for stages without CAR teardown. */
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_ebss = .;
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#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
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_shadow_size = (_ebss - _car_region_start) >> 3;
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REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE)
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#endif
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_car_unallocated_start = .;
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_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
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}
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. = _car_region_end;
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.car.mrc_var . (NOLOAD) : {
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. += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;
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}
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#if ENV_BOOTBLOCK
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_car_mtrr_end = .;
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_car_mtrr_start = _car_region_start;
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_car_mtrr_size = _car_mtrr_end - _car_mtrr_start;
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_car_mtrr_sz_log2 = 1 << LOG2CEIL(_car_mtrr_size);
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_car_mtrr_mask = ~(MAX(4096, _car_mtrr_sz_log2) - 1);
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#if !CONFIG(NO_XIP_EARLY_STAGES)
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_xip_program_sz_log2 = 1 << LOG2CEIL(_ebootblock - _bootblock);
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_xip_mtrr_mask = ~(MAX(4096, _xip_program_sz_log2) - 1);
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#endif
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_rom_mtrr_mask = ~(CACHE_ROM_SIZE - 1);
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_rom_mtrr_base = _rom_mtrr_mask;
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#endif
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/* Global variables are not allowed in romstage
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* This section is checked during stage creation to ensure
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* that there are no global variables present
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*/
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. = 0xffffff00;
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.illegal_globals . : {
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
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*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
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}
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_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
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#if CONFIG(PAGING_IN_CACHE_AS_RAM)
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_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
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#endif
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_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
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#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE)
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_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
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_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
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#endif
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