8950cfb66f
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
315 lines
8.7 KiB
C
315 lines
8.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <soc/iobp.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pch.h>
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#include <soc/ramstage.h>
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#include <soc/rcba.h>
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#include <soc/serialio.h>
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#include <soc/intel/broadwell/chip.h>
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/* Set D3Hot Power State in ACPI mode */
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static void serialio_enable_d3hot(struct resource *res)
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{
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u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
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reg32 |= PCH_PCS_PS_D3HOT;
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write32(res2mmio(res, PCH_PCS, 0), reg32);
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}
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static int serialio_uart_is_debug(struct device *dev)
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{
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#if CONFIG(INTEL_PCH_UART_CONSOLE)
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switch (dev->path.pci.devfn) {
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case PCH_DEVFN_UART0: /* UART0 */
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return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0);
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case PCH_DEVFN_UART1: /* UART1 */
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return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1);
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}
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#endif
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return 0;
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}
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/* Enable clock in PCI mode */
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static void serialio_enable_clock(struct resource *bar0)
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{
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u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
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reg32 |= SIO_REG_PPR_CLOCK_EN;
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write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
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}
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/* Put Serial IO D21:F0-F6 device into desired mode. */
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static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode)
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{
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u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
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/* Snoop select 1. */
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portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
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/* Set interrupt pin. */
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portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
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if (acpi_mode) {
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/* Enable ACPI interrupt mode. */
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portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
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/* Disable PCI config space. */
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portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS;
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}
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pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
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}
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/* Put Serial IO D23:F0 device into desired mode. */
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static void serialio_d23_mode(int acpi_mode)
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{
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u32 portctrl = 0;
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/* Snoop select 1. */
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pch_iobp_update(SIO_IOBP_PORTCTRL1, 0,
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SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1));
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if (acpi_mode) {
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/* Enable ACPI interrupt mode. */
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portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN;
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/* Disable PCI config space. */
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portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS;
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}
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pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl);
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}
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/* Enable LTR Auto Mode for D21:F1-F6. */
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static void serialio_d21_ltr(struct resource *bar0)
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{
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u32 reg;
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/* 1. Program BAR0 + 808h[2] = 0b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
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reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
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write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
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/* 2. Program BAR0 + 804h[1:0] = 00b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
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reg &= ~SIO_REG_PPR_RST_ASSERT;
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write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
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/* 3. Program BAR0 + 804h[1:0] = 11b */
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reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
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reg |= SIO_REG_PPR_RST_ASSERT;
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write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
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/* 4. Program BAR0 + 814h[31:0] = 00000000h */
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write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
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}
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/* Enable LTR Auto Mode for D23:F0. */
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static void serialio_d23_ltr(struct resource *bar0)
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{
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u32 reg;
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/* Program BAR0 + 1008h[2] = 1b */
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reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
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reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
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/* Program BAR0 + 1010h = 0x00000000 */
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
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/* Program BAR0 + 3Ch[30] = 1b */
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reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
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reg |= SIO_REG_SDIO_PPR_CMD12_B30;
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write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
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}
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/* Select I2C voltage of 1.8V or 3.3V. */
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static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
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{
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u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
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reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
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reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
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write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
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}
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/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
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static void serialio_init_once(int acpi_mode)
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{
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if (acpi_mode) {
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/* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
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RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5));
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}
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/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */
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pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
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/* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
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pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
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}
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static void serialio_init(struct device *dev)
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{
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config_t *config = config_of(dev);
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struct resource *bar0, *bar1;
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int sio_index = -1;
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u32 reg32;
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printk(BIOS_DEBUG, "Initializing Serial IO device\n");
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/* Ensure memory and bus master are enabled */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Find BAR0 and BAR1 */
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bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!bar0)
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return;
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bar1 = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (!bar1)
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return;
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if (!config->sio_acpi_mode)
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serialio_enable_clock(bar0);
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switch (dev->path.pci.devfn) {
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case PCH_DEVFN_SDMA: /* SDMA */
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sio_index = SIO_ID_SDMA;
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serialio_init_once(config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTB,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C0: /* I2C0 */
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sio_index = SIO_ID_I2C0;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C1: /* I2C1 */
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sio_index = SIO_ID_I2C1;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI0: /* SPI0 */
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sio_index = SIO_ID_SPI0;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI1: /* SPI1 */
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sio_index = SIO_ID_SPI1;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART0: /* UART0 */
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sio_index = SIO_ID_UART0;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART1: /* UART1 */
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sio_index = SIO_ID_UART1;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SDIO: /* SDIO */
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sio_index = SIO_ID_SDIO;
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serialio_d23_ltr(bar0);
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serialio_d23_mode(config->sio_acpi_mode);
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break;
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default:
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return;
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}
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if (config->sio_acpi_mode) {
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global_nvs_t *gnvs;
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/* Find ACPI NVS to update BARs */
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gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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printk(BIOS_ERR, "Unable to locate Global NVS\n");
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return;
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}
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/* Save BAR0 and BAR1 to ACPI NVS */
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gnvs->dev.bar0[sio_index] = (u32)bar0->base;
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gnvs->dev.bar1[sio_index] = (u32)bar1->base;
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/* Do not enable UART if it is used as debug port */
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if (!serialio_uart_is_debug(dev))
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gnvs->dev.enable[sio_index] = 1;
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/* Put device in D3hot state via BAR1 */
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if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
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serialio_enable_d3hot(bar1); /* all but SDMA */
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}
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}
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static void serialio_set_resources(struct device *dev)
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{
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pci_dev_set_resources(dev);
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#if CONFIG(INTEL_PCH_UART_CONSOLE)
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/* Update UART base address if used for debug */
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if (serialio_uart_is_debug(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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uartmem_setbaseaddr(res->base);
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}
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#endif
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}
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static struct device_operations device_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &serialio_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &serialio_init,
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.ops_pci = &broadwell_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x9c60, 0x9ce0, /* 0:15.0 - SDMA */
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0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */
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0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */
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0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */
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0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */
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0x9c63, 0x9ce3, /* 0:15.5 - UART0 */
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0x9c64, 0x9ce4, /* 0:15.6 - UART1 */
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0x9c35, 0x9cb5, /* 0:17.0 - SDIO */
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0
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};
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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