413e3da8c0
All code must agree on PCI enumeration for the CK804 device, define these only once. The definition in enable_usbdebug.c was different and was assumed incorrect. Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Tyan Computer
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* Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
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* Copyright (C) 2006,2007 AMD
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* Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/pci_ehci.h>
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#include <device/pci_def.h>
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#include "ck804.h"
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pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
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{
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return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
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}
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void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
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{
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u32 dword;
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/* Write the port number to 0x74[15:12]. */
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dword = pci_read_config32(dev, 0x74);
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dword &= ~(0xf << 12);
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dword |= (port << 12);
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pci_write_config32(dev, 0x74, dword);
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}
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void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
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{
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/* Set the EHCI BAR address. */
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pci_write_config32(dev, EHCI_BAR_INDEX, base);
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/* Enable access to the EHCI memory space registers. */
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pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
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}
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