4177db52a2
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
100 lines
3.1 KiB
Plaintext
100 lines
3.1 KiB
Plaintext
chip soc/intel/baytrail
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# SATA port enable mask (2 ports)
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register "sata_port_map" = "0x1"
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register "sata_ahci" = "0x1"
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register "ide_legacy_combined" = "0x0"
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# Route USB ports to XHCI
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register "usb_route_to_xhci" = "1"
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# USB Port Disable Mask
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register "usb2_port_disable_mask" = "0x0"
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register "usb3_port_disable_mask" = "0x0"
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# USB PHY settings
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# TODO: These values are from Baytrail and need tuned for Rambi board
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register "usb2_per_port_lane0" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
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register "usb2_per_port_lane1" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
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register "usb2_per_port_lane2" = "0x00049209"
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register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
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register "usb2_per_port_lane3" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
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# LPE audio codec settings
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register "lpe_codec_clk_freq" = "19" # 19.2MHz clock
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register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
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# SD Card controller
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register "sdcard_cap_low" = "0x036864b2"
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register "sdcard_cap_high" = "0x0"
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# Enable devices in ACPI mode
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register "scc_acpi_mode" = "1"
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register "lpss_acpi_mode" = "1"
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# Enable PIPEA as DP_C
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register "gpu_pipea_hotplug" = "6" # 6ms Pulse
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register "gpu_pipea_port_select" = "2" # DP_C
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register "gpu_pipea_power_cycle_delay" = "5" # 400ms
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register "gpu_pipea_power_on_delay" = "2000" # 200ms
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register "gpu_pipea_light_on_delay" = "10" # 1ms
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register "gpu_pipea_power_off_delay" = "500" # 50ms
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register "gpu_pipea_light_off_delay" = "2000" # 200ms
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register "gpu_pipea_backlight_pwm" = "0x400"
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# VR PS2 control
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register "vnn_ps2_enable" = "1"
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register "vcc_ps2_enable" = "1"
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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device pci 11.0 off end # SDIO
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device pci 12.0 on end # SD
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device pci 13.0 on end # SATA
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device pci 14.0 on end # XHCI
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device pci 15.0 on end # LPE
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device pci 17.0 on end # MMC
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device pci 18.0 on end # SIO_DMA1
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device pci 18.1 on end # I2C1
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 on end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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device pci 1b.0 on end # HDA
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device pci 1c.0 on end # PCIE_PORT1
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device pci 1c.1 on end # PCIE_PORT2
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device pci 1c.2 off end # PCIE_PORT3
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device pci 1c.3 off end # PCIE_PORT4
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device pci 1d.0 on end # EHCI
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device pci 1e.0 on end # SIO_DMA2
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device pci 1e.1 off end # PWM1
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device pci 1e.2 off end # PWM2
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device pci 1e.3 off end # HSUART1
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device pci 1e.4 off end # HSUART2
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device pci 1e.5 off end # SPI
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device pci 1f.0 on
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC Bridge
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device pci 1f.3 off end # SMBus
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end
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end
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