41a2c73b06
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
22 lines
578 B
Plaintext
22 lines
578 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
|
|
config NORTHBRIDGE_INTEL_I440BX
|
|
bool
|
|
select NO_MMCONF_SUPPORT
|
|
select HAVE_DEBUG_RAM_SETUP
|
|
select NO_CBFS_MCACHE
|
|
select LEGACY_SMP_INIT
|
|
|
|
config SDRAMPWR_4DIMM
|
|
bool
|
|
depends on NORTHBRIDGE_INTEL_I440BX
|
|
default n
|
|
help
|
|
This option affects how the SDRAMC register is programmed.
|
|
Memory clock signals will not be routed properly if this option
|
|
is set wrong.
|
|
|
|
If your board has 4 DIMM slots, you must use select this option, in
|
|
your Kconfig file of the board. On boards with 3 DIMM slots,
|
|
do _not_ select this option.
|