4247426be6
TEST=Compiled for and ran on spike; it booted as before. Change-Id: Id173643a3571962406f9191db248b206235dca35 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
22 lines
267 B
Plaintext
22 lines
267 B
Plaintext
config ARCH_RISCV
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bool
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default n
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config ARCH_BOOTBLOCK_RISCV
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bool
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default n
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select ARCH_RISCV
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select C_ENVIRONMENT_BOOTBLOCK
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config ARCH_VERSTAGE_RISCV
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bool
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default n
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config ARCH_ROMSTAGE_RISCV
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bool
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default n
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config ARCH_RAMSTAGE_RISCV
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bool
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default n
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