43a54184b0
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP SP SoCs (Granite Rapids SP and Sierra Forest SP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). TEST=Build on intel/beechnutcity CRB Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Gang Chen <gang.c.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
38 lines
921 B
Plaintext
38 lines
921 B
Plaintext
## SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/intel/xeon_sp/gnr
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# configure LPC generic IO decode ranges
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# [bits 31..24: reserved]
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# [bits 23..18: io decode address mask <7..2>]
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# [bits 17..16: reserved]
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# [bits 15..2 : io decode dword aligned address <15..2>]
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# [bit 1 : reserved]
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# [bit 0 : enabled]
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register "gen1_dec" = "0x00000CA1" # IPMI KCS
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# configure FSP debug settings
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register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
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device domain 0 on
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device pci 1f.0 on
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chip superio/common
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device pnp 2e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 2e.2 on # SUART1
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io 0x60 = 0x3f8 # PNP_IDX_IO0
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irq 0x70 = 4 # PNP_IDX_IRQ0
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end
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end
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end
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end
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chip drivers/ipmi
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device pnp ca2.0 on end # BMC KCS
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register "wait_for_bmc" = "1"
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register "bmc_boot_timeout" = "60"
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end
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end
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end
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end
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