43b6e2ed71
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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* Copyright (C) 2018 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/spi.h>
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#include <string.h>
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#include <drivers/spi/spi_winbond.h>
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/*
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* SPI lockdown configuration
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*/
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#define SPI_OPMENU_0 CMD_W25_WRSR /* Write Status Register */
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#define SPI_OPTYPE_0 SPI_OPTYPE_WR_NOADDR /* Write, no address */
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#define SPI_OPMENU_1 CMD_W25_PP /* BYPR: Byte Program */
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#define SPI_OPTYPE_1 SPI_OPTYPE_WR_ADDR /* Write, address required */
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#define SPI_OPMENU_2 CMD_W25_READ /* Read Data */
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#define SPI_OPTYPE_2 SPI_OPTYPE_RD_ADDR /* Read, address required */
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#define SPI_OPMENU_3 CMD_W25_RDSR /* Read Status Register */
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#define SPI_OPTYPE_3 SPI_OPTYPE_RD_NOADDR /* Read, no address */
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#define SPI_OPMENU_4 CMD_W25_SE /* Sector Erase */
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#define SPI_OPTYPE_4 SPI_OPTYPE_WR_ADDR /* Write, address required */
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#define SPI_OPMENU_5 CMD_W25_RDID /* Read ID */
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#define SPI_OPTYPE_5 SPI_OPTYPE_RD_NOADDR /* Read, no address */
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#define SPI_OPMENU_6 CMD_W25_BE /* BE: Block Erase */
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#define SPI_OPTYPE_6 SPI_OPTYPE_WR_ADDR /* Write, address required */
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#define SPI_OPMENU_7 CMD_W25_FAST_READ /* FAST: Fast Read */
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#define SPI_OPTYPE_7 SPI_OPTYPE_RD_ADDR /* Read, address required */
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#define SPI_OPPREFIX CMD_W25_WREN /* WREN only to be inline */
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/* with flashrom */
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
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#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
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static const struct spi_config spi_config = {
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.preop = CMD_W25_WREN,
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.optype = SPI_OPTYPE,
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.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
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.lvscc = SPI_VSCC,
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.uvscc = SPI_VSCC,
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};
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int mainboard_get_spi_config(struct spi_config *cfg)
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{
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memcpy(cfg, &spi_config, sizeof(*cfg));
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return 0;
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}
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