43b7f41678
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <device/path.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "bh720.h"
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static u32 bh720_read_pcr(u32 sdbar, u32 addr)
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{
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write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | addr);
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return read32((void *)(sdbar + BH720_MEM_RW_DATA));
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}
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static void bh720_write_pcr(u32 sdbar, u32 addr, u32 data)
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{
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write32((void *)(sdbar + BH720_MEM_RW_DATA), data);
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write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | addr);
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}
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static void bh720_rmw_pcr(u32 sdbar, u32 addr, u32 clear, u32 set)
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{
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u32 data = bh720_read_pcr(sdbar, addr);
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data &= ~clear;
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data |= set;
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bh720_write_pcr(sdbar, addr, data);
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}
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static void bh720_program_hs200_mode(struct device *dev)
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{
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u32 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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/* Enable Memory Access Function */
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write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
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bh720_write_pcr(sdbar, 0xd0, 0x80000000);
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/* Set EMMC VCCQ 1.8V PCR 0x308[4] */
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bh720_rmw_pcr(sdbar, BH720_PCR_EMMC_SETTING, 0, BH720_PCR_EMMC_SETTING_1_8V);
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/* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
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bh720_rmw_pcr(sdbar, BH720_PCR_DrvStrength_PLL, 0xffff << 16, 0x2510 << 16);
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/* Use PLL Base clock PCR 0x3E4[22] = 1 */
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bh720_rmw_pcr(sdbar, BH720_PCR_CSR, 0, BH720_PCR_CSR_EMMC_MODE_SEL);
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/* Disable Memory Access */
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bh720_write_pcr(sdbar, 0xd0, 0x80000001);
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write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
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}
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static void bh720_init(struct device *dev)
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{
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struct drivers_generic_bayhub_config *config = dev->chip_info;
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pci_dev_init(dev);
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if (config && config->power_saving) {
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/*
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* This procedure for enabling power-saving mode is from the
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* BayHub BIOS Implementation Guideline document.
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*/
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pci_write_config32(dev, BH720_PROTECT,
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BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
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pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
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pci_or_config32(dev, BH720_LINK_CTRL,
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BH720_LINK_CTRL_L0_ENABLE |
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BH720_LINK_CTRL_L1_ENABLE);
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pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
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pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
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BH720_MISC2_APSM_CLKREQ_L1 |
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BH720_MISC2_APSM_PHY_L1);
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pci_write_config32(dev, BH720_PROTECT,
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BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
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printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
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pci_read_config32(dev, BH720_LINK_CTRL));
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}
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if (config && !config->disable_hs200_mode)
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bh720_program_hs200_mode(dev);
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if (config && config->vih_tuning_value) {
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/* Tune VIH */
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u32 bh720_pcr_data;
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pci_write_config32(dev, BH720_PROTECT,
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BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
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bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
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bh720_pcr_data &= 0xFFFFFF00;
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bh720_pcr_data |= config->vih_tuning_value;
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pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
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pci_write_config32(dev, BH720_PROTECT,
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BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
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}
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}
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static struct device_operations bh720_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.ops_pci = &pci_dev_ops_pci,
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.init = bh720_init,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DID_O2_BH720,
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0
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};
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static const struct pci_driver bayhub_bh720 __pci_driver = {
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.ops = &bh720_ops,
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.vendor = PCI_VID_O2,
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.devices = pci_device_ids,
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};
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struct chip_operations drivers_generic_bayhub_ops = {
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CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge")
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};
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