44e310bc6c
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
116 lines
2.4 KiB
Plaintext
116 lines
2.4 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
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BOARD_PCENGINES_APU5
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_PI_00730F01
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select NORTHBRIDGE_AMD_PI_00730F01
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select SOUTHBRIDGE_AMD_PI_AVALON
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select DEFAULT_POST_ON_LPC
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select SUPERIO_NUVOTON_NCT5104D
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_8192
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select GENERIC_SPD_BIN
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select MAINBOARD_HAS_LPC_TPM
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select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_L1_SUB_STATE
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config MAINBOARD_DIR
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string
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default "pcengines/apu2"
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config VARIANT_DIR
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string
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default "apu2" if BOARD_PCENGINES_APU2
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default "apu3" if BOARD_PCENGINES_APU3
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default "apu4" if BOARD_PCENGINES_APU4
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default "apu5" if BOARD_PCENGINES_APU5
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config MAINBOARD_PART_NUMBER
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string
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default "apu2" if BOARD_PCENGINES_APU2
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default "apu3" if BOARD_PCENGINES_APU3
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default "apu4" if BOARD_PCENGINES_APU4
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default "apu5" if BOARD_PCENGINES_APU5
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config MAX_CPUS
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int
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default 4
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config HUDSON_LEGACY_FREE
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bool
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default y
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config AGESA_BINARY_PI_FILE
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string
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default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
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choice
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prompt "J19 pins 1-10"
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default APU2_PINMUX_UART_C
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config APU2_PINMUX_OFF_C
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bool "disable"
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config APU2_PINMUX_GPIO0
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bool "GPIO"
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depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
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BOARD_PCENGINES_APU4
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config APU2_PINMUX_UART_C
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bool "UART 0x3e8"
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endchoice
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choice
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prompt "J19 pins 11-20"
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default APU2_PINMUX_UART_D
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config APU2_PINMUX_OFF_D
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bool "disable"
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config APU2_PINMUX_GPIO1
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bool "GPIO"
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depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
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BOARD_PCENGINES_APU4
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config APU2_PINMUX_UART_D
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bool "UART 0x2e8"
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endchoice
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config DIMM_SPD_SIZE
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int
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default 128
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config AGESA_USE_1_0_0_4_HEADER
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bool
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default y
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help
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Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
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impossible to use the newest blob. Using an older 1.0.0.4 blob
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workarounds the problem, however some headers changes between blob
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revisions. This option removes the changes in headers introduced
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with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
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endif # BOARD_PCENGINES_APU2
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