45a1c949cb
Instead of calling out the gpio index and port numbers use real names. It's semantically clearer and there's only one place to adjust the hardware values. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted. Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215542 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9027 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
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#define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
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#include <soc/nvidia/tegra132/gpio.h>
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/* Board ID definitions. */
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enum {
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BOARD_ID_PROTO_0 = 0,
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BOARD_ID_PROTO_1 = 1,
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BOARD_ID_EVT = 2,
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BOARD_ID_DVT = 3,
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BOARD_ID_PVT = 4,
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BOARD_ID_MP = 5,
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};
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enum {
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/* Board ID related GPIOS. */
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BD_ID0 = GPIO(Q3),
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BD_ID1 = GPIO(Q4),
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/* LTE modem related GPIOs */
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MODEM_RESET = GPIO(S3),
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MODEM_PWR_ON = GPIO(S4),
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MDM_DET = GPIO(V1),
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/* Warm reset */
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AP_SYS_RESET_L = GPIO(I5),
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/* Write Protect */
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SPI_1V8_WP_L = GPIO(R1),
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WRITE_PROTECT_L = SPI_1V8_WP_L,
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WRITE_PROTECT_L_INDEX = GPIO_R1_INDEX,
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/* Power Button */
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BTN_AP_PWR_L = GPIO(Q0),
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POWER_BUTTON_L = BTN_AP_PWR_L,
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POWER_BUTTON_L_INDEX = GPIO_Q0_INDEX,
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};
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#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ */
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