45e4ab4a66
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pnp_def.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <superio/winbond/common/winbond.h>
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void mainboard_pch_lpc_setup(void)
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{
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/* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
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/* Enable KBC on 0x06/0x64 (KBC),
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* EC on 0x62/0x66 (MC),
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* EC on 0x20c-0x20f (GAMEH),
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* Super I/O on 0x2e/0x2f (CNF1),
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* COM1/COM3 decode ranges. */
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pci_write_config16(PCH_LPC_DEV, LPC_EN,
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KBC_LPC_EN | MC_LPC_EN |
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CNF1_LPC_EN | GAMEH_LPC_EN |
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COMA_LPC_EN | COMB_LPC_EN);
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}
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void bootblock_mainboard_early_init(void)
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{
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int lvds_3v = 0; /* 0 (5V) or 1 (3V3) */
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int dis_bl_inv = 1; /* backlight inversion: 1 = disabled, 0 = enabled */
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const pnp_devfn_t dev = PNP_DEV(0x2e, 0x9);
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pnp_enter_conf_state(dev);
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pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */
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pnp_write_config(dev, PNP_IDX_EN, 0x03); /* Enable GPIO2+3 */
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pnp_write_config(dev, 0x2a, 0x01); /* Pins 62, 63, 65, 66 are
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GPIO27, 26, 25, 24 */
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pnp_write_config(dev, 0x2c, 0xc3); /* Pin 90 is GPIO32,
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Pins 78~85 are UART B */
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pnp_write_config(dev, 0x2d, 0x00); /* Pins 67, 68, 70~73, 75, 77 are
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GPIO57~50 */
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pnp_set_logical_device(dev);
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/* Values can only be changed, when devices are enabled. */
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pnp_write_config(dev, 0xe3, 0xdd); /* GPIO2 bits 1, 5 are output */
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pnp_write_config(dev, 0xe4, (dis_bl_inv << 5) | (lvds_3v << 1)); /* GPIO2 bits 1, 5 */
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/* Disable suspend LED during normal operation */
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pnp_write_config(dev, PNP_IDX_MSC3, 0x40);
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pnp_exit_conf_state(dev);
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power USB oc pin */
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{ 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */
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{ 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */
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};
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void mainboard_early_init(int s3resume)
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{
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/* Enable PEG10 (1x16) */
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pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
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pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) |
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DEVEN_PEG10);
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}
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