Usha P 46445155ea soc/intel/common: Set controller state to active in uart init ...

Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.

One more argument struct device *dev has been added
to uart_lpss_init function for the same.

BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
     sequence in CML and ICL platforms.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2019-07-24 03:05:45 +00:00

..

apollolake

soc/intel: Expand SA_DEV_ROOT for ramstage

2019-07-21 18:58:01 +00:00

baytrail

soc/intel: Use config_of()

2019-07-18 15:25:35 +00:00

braswell

soc/intel: Use config_of()

2019-07-18 15:25:35 +00:00

broadwell

soc/intel/broadwell: Change variable back to u32

2019-07-22 20:36:56 +00:00

cannonlake

soc/intel: Expand SA_DEV_ROOT for ramstage

2019-07-21 18:58:01 +00:00

common

soc/intel/common: Set controller state to active in uart init

2019-07-24 03:05:45 +00:00

denverton_ns

soc/intel: Expand SA_DEV_ROOT for ramstage

2019-07-21 18:58:01 +00:00

fsp_baytrail

soc/intel: Use config_of()

2019-07-18 15:25:35 +00:00

fsp_broadwell_de

soc/intel: Use config_of()

2019-07-18 15:25:35 +00:00

icelake

soc/intel: Expand SA_DEV_ROOT for ramstage

2019-07-21 18:58:01 +00:00

quark

soc/intel: Use config_of()

2019-07-18 15:25:35 +00:00

skylake

soc/intel: Expand SA_DEV_ROOT for ramstage

2019-07-21 18:58:01 +00:00

Kconfig

cbfstool: Drop update-fit option

2019-06-24 09:45:00 +00:00