470ca5714f
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 4, 29
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*/
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#include <bootstate.h>
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#include <commonlib/console/post_codes.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <spi-generic.h>
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static void pch_finalize(void)
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{
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config_t *config;
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/* TCO Lock down */
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tco_lockdown();
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/* TODO: Add Thermal Configuration */
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*
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* SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
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* just required to get to chip config. PCH_DEV_PMC is hidden by this
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* point and hence removed from the root bus. pcidev_path_on_root thus
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* returns NULL for PCH_DEV_PMC device.
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*/
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config = config_of_soc();
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if (config->PmTimerDisabled)
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pmc_disable_acpi_timer();
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pmc_clear_pmcon_sts();
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}
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static void tbt_finalize(void)
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{
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int i;
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const struct device *dev;
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/* Disable Thunderbolt PCIe root ports bus master */
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for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
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dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
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if (dev)
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pci_dev_disable_bus_master(dev);
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}
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}
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static void soc_finalize(void *unused)
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{
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize();
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apm_control(APM_CNT_FINALIZE);
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tbt_finalize();
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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