4913d8aed0
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <stdint.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <arch/bert_storage.h>
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#include <soc/northbridge.h>
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#include <soc/iomap.h>
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#include <amdblocks/acpimmio.h>
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void backup_top_of_low_cacheable(uintptr_t ramtop)
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{
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biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
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}
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uintptr_t restore_top_of_low_cacheable(void)
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{
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return biosram_read32(BIOSRAM_CBMEM_TOP);
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}
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#if CONFIG(ACPI_BERT)
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#if CONFIG_SMM_TSEG_SIZE == 0x0
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#define BERT_REGION_MAX_SIZE 0x100000
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#else
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/* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
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#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
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#endif
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#else
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#define BERT_REGION_MAX_SIZE 0
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#endif
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void bert_reserved_region(void **start, size_t *size)
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{
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if (CONFIG(ACPI_BERT))
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*start = cbmem_top();
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else
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start = NULL;
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*size = BERT_REGION_MAX_SIZE;
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}
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void *cbmem_top(void)
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{
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msr_t tom = rdmsr(TOP_MEM);
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if (!tom.lo)
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return 0;
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/* 8MB alignment to keep MTRR usage low */
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return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
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- CONFIG_SMM_TSEG_SIZE
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- BERT_REGION_MAX_SIZE, 8*MiB);
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}
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static uintptr_t smm_region_start(void)
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{
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return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE;
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}
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static size_t smm_region_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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/*
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* For data stored in TSEG, ensure TValid is clear so R/W access can reach
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* the DRAM when not in SMM.
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*/
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static void clear_tvalid(void)
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{
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msr_t hwcr = rdmsr(HWCR_MSR);
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msr_t mask = rdmsr(SMM_MASK_MSR);
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int tvalid = !!(mask.lo & SMM_TSEG_VALID);
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if (hwcr.lo & SMM_LOCK) {
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if (!tvalid) /* not valid but locked means still accessible */
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return;
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printk(BIOS_ERR, "Error: can't clear TValid, already locked\n");
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return;
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}
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mask.lo &= ~SMM_TSEG_VALID;
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wrmsr(SMM_MASK_MSR, mask);
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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static int once;
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*start = smm_region_start();
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*size = smm_region_size();
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if (!once) {
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clear_tvalid();
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once = 1;
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}
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}
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