4913d8aed0
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/smm.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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void *cbmem_top(void)
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{
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const config_t *config;
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void *tolum = (void *)sa_get_tseg_base();
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if (!CONFIG(SOC_INTEL_GLK))
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return tolum;
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config = config_of_path(PCH_DEVFN_LPC);
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/* FSP allocates 2x PRMRR Size Memory for alignment */
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if (config->sgx_enable)
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tolum -= config->PrmrrSize * 2;
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return tolum;
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = sa_get_tseg_base();
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*size = sa_get_tseg_size();
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}
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