491c016d77
On Apollolake CPU memory mapping is similar to previous SoC, and we place CBMEM right under TSEG. Change-Id: I606f690449ba98af6e9fc3074d677c7287892164 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13883 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
36 lines
974 B
Makefile
36 lines
974 B
Makefile
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
|
|
|
|
subdirs-y += ../../../cpu/intel/microcode
|
|
subdirs-y += ../../../cpu/intel/turbo
|
|
subdirs-y += ../../../cpu/x86/lapic
|
|
subdirs-y += ../../../cpu/x86/mtrr
|
|
subdirs-y += ../../../cpu/x86/smm
|
|
subdirs-y += ../../../cpu/x86/tsc
|
|
|
|
bootblock-y += bootblock/bootblock.c
|
|
bootblock-y += bootblock/cache_as_ram.S
|
|
bootblock-y += bootblock/bootblock.c
|
|
bootblock-y += gpio.c
|
|
bootblock-y += mmap_boot.c
|
|
bootblock-y += placeholders.c
|
|
bootblock-y += tsc_freq.c
|
|
bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
|
|
|
|
romstage-y += placeholders.c
|
|
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
|
|
romstage-y += gpio.c
|
|
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
|
|
romstage-y += memmap.c
|
|
romstage-y += mmap_boot.c
|
|
|
|
smm-y += placeholders.c
|
|
ramstage-y += placeholders.c
|
|
ramstage-y += gpio.c
|
|
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
|
|
ramstage-y += memmap.c
|
|
ramstage-y += mmap_boot.c
|
|
|
|
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
|
|
|
|
endif
|