4a8cd72c05
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
32 lines
652 B
C
32 lines
652 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/tsc.h>
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#include <console/console.h>
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static unsigned long mhz;
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unsigned long tsc_freq_mhz(void)
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{
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msr_t msr;
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uint8_t cpufid;
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uint8_t cpudid;
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uint8_t high_state;
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if (mhz)
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return mhz;
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high_state = rdmsr(PS_LIM_REG).lo & 0x7;
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msr = rdmsr(PSTATE_0_MSR + high_state);
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if (!(msr.hi & 0x80000000))
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die("Unknown error: cannot determine P-state 0\n");
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cpufid = (msr.lo & 0x3f);
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cpudid = (msr.lo & 0x1c0) >> 6;
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mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
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return mhz;
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}
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