This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
		
			
				
	
	
		
			58 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			58 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * This file is part of the coreboot project.
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|  *
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|  * Copyright (C) 2013 Google Inc.
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|  * Copyright (C) 2015-2016 Intel Corp.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; version 2 of the License.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  */
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| 
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| #include <cpu/x86/smm.h>
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| #include <cpu/intel/em64t100_save_state.h>
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| #include <intelblocks/smihandler.h>
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| #include <soc/gpio.h>
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| #include <soc/iomap.h>
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| #include <soc/pci_devs.h>
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| #include <soc/pm.h>
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| 
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| int smihandler_soc_disable_busmaster(pci_devfn_t dev)
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| {
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| 	if (dev == PCH_DEV_PMC)
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| 		return 0;
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| 	return 1;
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| }
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| 
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| const struct smm_save_state_ops *get_smm_save_state_ops(void)
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| {
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| 	return &em64t100_smm_ops;
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| }
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| 
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| /* SMI handlers that should be serviced in SCI mode too. */
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| uint32_t smihandler_soc_get_sci_mask(void)
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| {
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| 	uint32_t sci_mask =
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| 		SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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| 		SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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| 
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| 	return sci_mask;
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| }
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| 
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| const smi_handler_t southbridge_smi[32] = {
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| 	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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| 	[APM_STS_BIT] = smihandler_southbridge_apmc,
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| 	[PM1_STS_BIT] = smihandler_southbridge_pm1,
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| 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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| 	[TCO_STS_BIT] = smihandler_southbridge_tco,
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| 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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| #if CONFIG(SOC_ESPI)
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| 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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| #endif
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| };
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