1eae39f4cd
There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
73 lines
1.7 KiB
PHP
73 lines
1.7 KiB
PHP
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Pushes a 32-bit register onto the stack.
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*
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* There are two possible code sections where this code can be included:
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* .code32 and .code64
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*
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* Doing a `push %eax` while in a .code64 section will result in a compiler
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* error. This macro manually pushes the 32-bit register onto the stack so we
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* can share the code between 32 and 64 bit builds.
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*/
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.macro pushr reg:req
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#if ENV_X86_64
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movl $0, -4(%esp)
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movl \reg, -8(%esp)
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sub $8, %esp
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#else
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push \reg
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#endif
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.endm
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/* Push struct cpu_info */
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.macro push_cpu_info index=$0
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pushr \index /* index (size_t) */
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pushr $0 /* *cpu */
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.endm
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/* Push struct per_cpu_segment_data */
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.macro push_per_cpu_segment_data cpu_info_pointer=%esp
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pushr \cpu_info_pointer /* *cpu_info */
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.endm
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/*
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* Sets the base address in the segment descriptor array.
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*
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* A segment descriptor has the following structure:
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* struct {
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* uint16_t segment_limit_0_15;
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* uint16_t base_address_0_15;
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* uint8_t base_address_16_23;
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* uint8_t attrs[2];
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* uint8_t base_address_24_31;
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* };
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*
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* @desc_array: Address of the descriptor table
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* @base: Address to set in the descriptor
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* @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a
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* register if specified.
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*
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* Clobbers %eax, %ebx.
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*/
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.macro set_segment_descriptor_base desc_array:req, base:req, desc_index
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mov \base, %eax
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mov \desc_array, %ebx
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.ifb \desc_index
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movw %ax, 2(%ebx)
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shr $16, %eax
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movb %al, 4(%ebx)
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shr $8, %eax
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movb %al, 7(%ebx)
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.else
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movw %ax, 2(%ebx, \desc_index, 8)
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shr $16, %eax
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movb %al, 4(%ebx, \desc_index, 8)
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shr $8, %eax
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movb %al, 7(%ebx, \desc_index, 8)
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.endif
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.endm
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