dfc6451830
When S0ix support is enabled it is always advertised to the OS that it is the preferred suspend method via the FADT feature flag. This config prevents the feature flag from being set, indicating to the OS that S3 suspend is the preferred sleep method. Test: `/sys/power/mem_sleep` defaults to "deep" on system76/darp8. Change-Id: Ife98166338c5457fb2c7dad81a30e54f487495f6 Signed-off-by: Tim Crawford <tcrawford@system76.com>
468 lines
12 KiB
C
468 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <drivers/intel/gma/gma.h>
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#include <gpio.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/xhci.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <soc/sata.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
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#include <soc/gpio_defs_cnp_h.h>
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#else
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#include <soc/gpio_defs.h>
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#endif
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#define SOC_INTEL_CML_UART_DEV_MAX 3
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#define SOC_INTEL_CML_SATA_DEV_MAX 8
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enum chip_pl2_4_cfg {
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baseline,
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performance,
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value_not_set /* vr_config internal use only */
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};
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struct soc_intel_cannonlake_config {
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/* Common struct containing soc config data required by common code */
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struct soc_intel_common_config common_soc_config;
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/* Common struct containing power limits configuration information */
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struct soc_power_limits_config power_limits_config;
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form GPP_[A:G] or GPD. */
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uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* S0ix configuration */
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/* Enable S0iX support */
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bool s0ix_enable;
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/* Enable Audio DSP oscillator qualification for S0ix */
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bool cppmvric2_adsposcdis;
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/* Enable DPTF support */
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bool dptf_enable;
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enum {
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MAX_PC_DEFAULT = 0,
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MAX_PC0_1 = 1,
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MAX_PC2 = 2,
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MAX_PC3 = 3,
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MAX_PC6 = 4,
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MAX_PC7 = 5,
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MAX_PC7S = 6,
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MAX_PC8 = 7,
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MAX_PC9 = 8,
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MAX_PC10 = 9,
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} max_package_c_state;
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/* Deep SX enable for both AC and DC */
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bool deep_s3_enable_ac;
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bool deep_s3_enable_dc;
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bool deep_s5_enable_ac;
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bool deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
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* DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
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uint32_t deep_sx_config;
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/* TCC activation offset */
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uint32_t tcc_offset;
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/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
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* For CNL, options are as following
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* When enabled, memory will be training at three different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
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* For WHL/CFL/CML options are as following
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* When enabled, memory will be training at two different frequencies.
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* 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/
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enum {
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SaGv_Disabled,
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SaGv_FixedLow,
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SaGv_FixedHigh,
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SaGv_Enabled,
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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bool RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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/* Wake Enable Bitmap for USB2 ports */
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uint16_t usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* USB2 PHY power gating */
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bool PchUsb2PhySusPgDisable;
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/* SATA related */
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enum {
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SATA_AHCI,
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SATA_RAID,
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} SataMode;
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/* SATA devslp pad reset configuration */
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enum {
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SataDevSlpResumeReset = 1,
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SataDevSlpHostDeepReset = 3,
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SataDevSlpPlatformReset = 5,
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SataDevSlpDswReset = 7
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} SataDevSlpRstConfig;
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bool SataSalpSupport;
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bool SataPortsEnable[8];
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bool SataPortsDevSlp[8];
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uint8_t SataPortsDevSlpResetConfig[8];
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bool SataPortsHotPlug[8];
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/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
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bool SlpS0WithGbeSupport;
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/* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */
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bool PchPmSlpS0VmRuntimeControl;
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/* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */
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bool PchPmSlpS0Vm070VSupport;
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/* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */
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bool PchPmSlpS0Vm075VSupport;
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/* Audio related */
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bool PchHdaDspEnable;
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/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
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bool PchHdaAudioLinkHda;
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bool PchHdaIDispCodecDisconnect;
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bool PchHdaAudioLinkDmic0;
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bool PchHdaAudioLinkDmic1;
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bool PchHdaAudioLinkSsp0;
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bool PchHdaAudioLinkSsp1;
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bool PchHdaAudioLinkSsp2;
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bool PchHdaAudioLinkSndw1;
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bool PchHdaAudioLinkSndw2;
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bool PchHdaAudioLinkSndw3;
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bool PchHdaAudioLinkSndw4;
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/* PCIe Root Ports */
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bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/* PCIe output clocks type to PCIe devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
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/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
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* clksrc. */
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
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/* PCIe LTR(Latency Tolerance Reporting) mechanism */
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bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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/* Implemented as slot or built-in? */
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bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
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/* Enable/Disable HotPlug support for Root Port */
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bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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/*
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* Enable/Disable AER (Advanced Error Reporting) for Root Port
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* 0: Disable AER
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* 1: Enable AER
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*/
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bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP ASPM, ASPM support for the root port */
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enum {
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AspmDefault,
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AspmDisabled,
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AspmL0s,
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AspmL1,
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AspmL0sL1,
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AspmAutoConfig,
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} PcieRpAspm[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP Max Payload, Max Payload Size supported */
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enum {
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RpMaxPayload_128,
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RpMaxPayload_256,
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} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
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/* eMMC and SD */
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bool ScsEmmcHs400Enabled;
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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bool EmmcHs400DllNeed;
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/* 0-39: number of active delay for RX strobe, unit is 125 psec */
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uint8_t EmmcHs400RxStrobeDll1;
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/* 0-78: number of active delay for TX data, unit is 125 psec */
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uint8_t EmmcHs400TxDataDll;
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/* Enable/disable SD card write protect pin configuration on CML */
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bool ScsSdCardWpPinEnabled;
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/* Heci related */
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bool DisableHeciRetry;
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/* Gfx related */
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bool SkipExtGfxScan;
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bool Device4Enable;
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/* CPU PL2/4 Config
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* Performance: Maximum PLs for maximum performance.
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* Baseline: Baseline PLs for balanced performance at lower power.
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*/
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enum chip_pl2_4_cfg cpu_pl2_4_cfg;
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/* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced */
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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/* Enables support for Teton Glacier hybrid storage device */
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bool TetonGlacierMode;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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bool eist_enable;
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/* Enable C6 DRAM */
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bool enable_c6dram;
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/*
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* SLP_S3 Minimum Assertion Width Policy
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* 1 = 60us
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* 2 = 1ms (default)
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* 3 = 50ms
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* 4 = 2s
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*/
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uint8_t PchPmSlpS3MinAssert;
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/*
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* SLP_S4 Minimum Assertion Width Policy
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* 1 = 1s
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* 2 = 2s
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* 3 = 3s
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* 4 = 4s (default)
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*/
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uint8_t PchPmSlpS4MinAssert;
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/*
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* SLP_SUS Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 500ms
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* 3 = 1s (default)
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* 4 = 4s
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*/
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uint8_t PchPmSlpSusMinAssert;
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/*
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* SLP_A Minimum Assertion Width Policy
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* 1 = 0ms
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* 2 = 4s
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* 3 = 98ms (default)
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* 4 = 2s
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*/
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uint8_t PchPmSlpAMinAssert;
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/*
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* PCH PM Reset Power Cycle Duration
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* 0 = 4s
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* 1 = 1s
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* 2 = 2s
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* 3 = 3s
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* 4 = 4s (default)
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*
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* NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
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* stretch duration programmed in the following registers -
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* - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
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* - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
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* - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
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* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
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*/
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uint8_t PchPmPwrCycDur;
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/*
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* SerialIO device mode selection:
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*
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* Device index:
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* PchSerialIoIndexI2C0
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* PchSerialIoIndexI2C1
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* PchSerialIoIndexI2C2
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* PchSerialIoIndexI2C3
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* PchSerialIoIndexI2C4
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* PchSerialIoIndexI2C5
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* PchSerialIoIndexSPI0
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* PchSerialIoIndexSPI1
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* PchSerialIoIndexSPI2
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* PchSerialIoIndexUART0
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* PchSerialIoIndexUART1
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* PchSerialIoIndexUART2
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*
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* Mode select:
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* For Cannonlake PCH following values are supported:
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* PchSerialIoNotInitialized
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* PchSerialIoDisabled
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* PchSerialIoPci
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* PchSerialIoAcpi
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* PchSerialIoHidden
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* PchSerialIoMax
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*
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* For Cometlake following values are supported:
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* PchSerialIoNotInitialized
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* PchSerialIoDisabled,
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* PchSerialIoPci,
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* PchSerialIoHidden,
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* PchSerialIoLegacyUart,
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* PchSerialIoSkipInit,
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* PchSerialIoMax
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*
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* NOTE:
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* PchSerialIoNotInitialized is not an option provided by FSP, this
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* option is default selected in case devicetree doesn't fill this param
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* In case PchSerialIoNotInitialized is selected or an invalid value is
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* provided from devicetree, coreboot will configure device into PCI
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* mode by default.
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*
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*/
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uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
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enum serirq_mode serirq_mode;
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/* GPIO SD card detect pin */
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unsigned int sdcard_cd_gpio;
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/* Enable Pch iSCLK */
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bool pch_isclk;
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/*
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* Acoustic Noise Mitigation
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* 0b - Disable
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* 1b - Enable noise mitigation
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*/
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bool AcousticNoiseMitigation;
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/*
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* Disable Fast Package C-state ramping
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* Need to set AcousticNoiseMitigation = '1' first
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* 0b - Enabled
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* 1b - Disabled
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*/
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bool FastPkgCRampDisableIa;
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bool FastPkgCRampDisableGt;
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bool FastPkgCRampDisableSa;
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bool FastPkgCRampDisableFivr;
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/*
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* Adjust the VR slew rates
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* Need to set AcousticNoiseMitigation = '1' first
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* 000b - Fast/2
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* 001b - Fast/4
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* 010b - Fast/8
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* 011b - Fast/16
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*/
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uint8_t SlowSlewRateForIa;
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uint8_t SlowSlewRateForGt;
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uint8_t SlowSlewRateForSa;
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uint8_t SlowSlewRateForFivr;
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/* SATA Power Optimizer */
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bool satapwroptimize;
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/* SATA Gen3 Strength */
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struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX];
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/* Enable or disable eDP device */
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bool DdiPortEdp;
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/* Enable or disable HPD of DDI port B/C/D/F */
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bool DdiPortBHpd;
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bool DdiPortCHpd;
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bool DdiPortDHpd;
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bool DdiPortFHpd;
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/* Enable or disable DDC of DDI port B/C/D/F */
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bool DdiPortBDdc;
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bool DdiPortCDdc;
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bool DdiPortDDdc;
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bool DdiPortFDdc;
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/* Unlock all GPIO Pads */
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bool PchUnlockGpioPads;
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/* Enable GBE wakeup */
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bool LanWakeFromDeepSx;
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bool WolEnableOverride;
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#if !CONFIG(SOC_INTEL_COMETLAKE)
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uint32_t VrPowerDeliveryDesign;
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#endif
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/*
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* Override GPIO PM configuration:
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* 0: Use FSP default GPIO PM program,
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* 1: coreboot to override GPIO PM program
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*/
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bool gpio_override_pm;
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/*
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* GPIO PM configuration: 0 to disable, 1 to enable power gating
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* Bit 6-7: Reserved
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* Bit 5: MISCCFG_GPSIDEDPCGEN
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* Bit 4: MISCCFG_GPRCOMPCDLCGEN
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* Bit 3: MISCCFG_GPRTCDLCGEN
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* Bit 2: MISCCFG_GSXLCGEN
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* Bit 1: MISCCFG_GPDPCGEN
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* Bit 0: MISCCFG_GPDLCGEN
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*/
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uint8_t gpio_pm[TOTAL_GPIO_COMM];
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/*
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* Override CPU flex ratio value:
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* CPU ratio value controls the maximum processor non-turbo ratio.
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* Valid Range 0 to 63.
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*
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* In general descriptor provides option to set default cpu flex ratio.
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* Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
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* That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
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*
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* Only override CPU flex ratio if don't want to boot with non-turbo max.
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*/
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uint8_t cpu_ratio_override;
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struct i915_gpu_panel_config panel_cfg;
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struct i915_gpu_controller_info gfx;
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/* Disable CPU Turbo in IA32_MISC_ENABLE */
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bool cpu_turbo_disable;
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bool disable_vmx;
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/*
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* Used with `s0ix_enable` to indicate S3 is the preferred suspend
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* method via the FADT feature flag.
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* Default is set to false, using S0ix for suspend.
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* Set this to true to indicate to the OS that S3 should be used.
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*/
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bool prefer_s3_suspend;
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};
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typedef struct soc_intel_cannonlake_config config_t;
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#endif
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