Lee Leahy 4cfde2a389 arch/x86: Generate a map file for the postcar stage ...

Place a map file for the postcar stage and place it into
build/cbfs/fallback.

TEST=Build and run on Galileo Gen2

Change-Id: I349c06e3c610db5b3f2511083208db27110c34d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15845
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-07-26 16:16:37 +02:00

..

acpi

arch/x86: provide common Intel ACPI hardware definitions

2016-07-15 08:31:21 +02:00

arch

arch/x86: Generate a map file for the postcar stage

2016-07-26 16:16:37 +02:00

commonlib

cbmem: share additional time stamps IDs

2016-07-20 22:09:24 +02:00

console

console/post: be explicit about conditional cmos_post_log() compiling

2016-05-25 18:04:11 +02:00

cpu

intel car: Use MTRR WRPROT type for XIP cache

2016-07-26 12:38:01 +02:00

device

device: i2c: Add support for I2C bus operations

2016-06-09 17:05:40 +02:00

drivers

drivers/elog: put back 4KiB limit

2016-07-26 15:35:37 +02:00

ec

ec/google/chromeec: provide common SMI handler helpers

2016-07-15 08:35:29 +02:00

include

drivers/uart: Enable debug serial output during postcar

2016-07-25 23:28:32 +02:00

lib

lib: Don't require ULZMA compression for postcar

2016-07-26 04:53:33 +02:00

mainboard

google/gru: Change UART _Static_assert() condition to #if

2016-07-25 18:57:32 +02:00

northbridge

intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE

2016-07-26 07:09:24 +02:00

soc

intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT

2016-07-25 18:58:38 +02:00

southbridge

timestamp: Drop duplicate TS_END_ROMSTAGE entries

2016-07-21 15:36:00 +02:00

superio

sio/winbond/w83667hg-a: Add pinmux defines for UART B

2016-05-29 19:34:54 +02:00

vendorcode

google/chromeos: Add support for saving recovery reason across reboot

2016-07-25 18:57:15 +02:00

Kconfig

src/lib: Enable display of cbmem during romstage and postcar

2016-07-26 01:18:09 +02:00