4d372c7353
This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
79 lines
1.9 KiB
Plaintext
79 lines
1.9 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config CPU_AMD_PI
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bool
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default y if CPU_AMD_PI_00630F01
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default y if CPU_AMD_PI_00730F01
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default y if CPU_AMD_PI_00660F01
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default n
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select DRIVERS_AMD_PI
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER
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select SMM_ASEG
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if CPU_AMD_PI
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config BINARYPI_LEGACY_WRAPPER
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def_bool n
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config XIP_ROM_SIZE
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hex
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default 0x100000
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help
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Overwride the default write through caching size as 1M Bytes.
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On some AMD platforms, one socket supports 2 or more kinds of
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processor family, compiling several CPU families agesa code
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will increase the romstage size.
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In order to execute romstage in place on the flash ROM,
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more space is required to be set as write through caching.
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config UDELAY_LAPIC_FIXED_FSB
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int
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default 200
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# TODO: Sync these with definitions in PI vendorcode.
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# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
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# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
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config DCACHE_RAM_BASE
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hex
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default 0x30000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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config S3_DATA_POS
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hex
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default 0xFFFF0000
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config S3_DATA_SIZE
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int
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default 32768
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endif # CPU_AMD_PI
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source src/cpu/amd/pi/00630F01/Kconfig
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source src/cpu/amd/pi/00730F01/Kconfig
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source src/cpu/amd/pi/00660F01/Kconfig
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