4d7d25f38a
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
108 lines
2.3 KiB
Plaintext
108 lines
2.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if BOARD_INTEL_MOHONPEAK
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_FSP_RANGELEY
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select SOUTHBRIDGE_INTEL_FSP_RANGELEY
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select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select MMCONF_SUPPORT
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select POST_IO
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select DEFAULT_POST_DEVICE_LPC
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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config MAINBOARD_DIR
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string
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default intel/mohonpeak
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config INCLUDE_ME
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bool
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default n
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config LOCK_MANAGEMENT_ENGINE
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bool
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default n
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config MAINBOARD_PART_NUMBER
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string
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default "Mohon Peak CRB"
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 16
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config FSP_FILE
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string
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default "../intel/fsp/rangeley/FvFsp.bin"
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config CBFS_SIZE
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hex
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default 0x00200000
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config DRIVERS_PS2_KEYBOARD
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bool
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default n
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config CONSOLE_POST
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bool
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default y
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config ENABLE_FSP_FAST_BOOT
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bool
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depends on HAVE_FSP_BIN
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default y
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config VIRTUAL_ROM_SIZE
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hex
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depends on ENABLE_FSP_FAST_BOOT
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default 0x400000
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config FSP_PACKAGE_DEFAULT
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bool "Configure defaults for the Intel FSP package"
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default n
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config UART_FOR_CONSOLE
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int
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default 1
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help
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The Mohon Peak board uses COM2 (2f8) for the serial console.
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config SEABIOS_MALLOC_UPPERMEMORY
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bool
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default n
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help
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The Avoton/Rangeley chip does not allow devices to write into the 0xe000
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segment. This means that USB/SATA devices will not work in SeaBIOS unless
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we put the SeaBIOS buffer area down in the 0x9000 segment.
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endif # BOARD_INTEL_MOHONPEAK
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