4d94ae4cfb
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I34bd5147bc1763416f8c875828cd6ee5c2a465ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <boardid.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/soc_services.h>
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#include <soc/usb.h>
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#include <soc/blsp.h>
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#include <symbols.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "mmu.h"
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#define USB_ENABLE_GPIO 51
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static void setup_usb(void)
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{
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usb_clock_config();
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setup_usb_host1();
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}
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static void mainboard_init(struct device *dev)
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{
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/* disable mmu and d-cache before setting up secure world.*/
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dcache_mmu_disable();
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start_tzbsp();
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/* Setup mmu and d-cache again as non secure entries. */
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setup_mmu(DRAM_INITIALIZED);
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setup_usb();
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if (CONFIG(CHROMEOS)) {
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/* Copy WIFI calibration data into CBMEM. */
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cbmem_add_vpd_calibration_data();
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}
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/*
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* Make sure bootloader can issue sounds The frequency is calculated
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* as "<frame_rate> * <bit_width> * <channels> * 4", i.e.
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*
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* 48000 * 2 * 16 * 4 = 6144000
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*/
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//audio_clock_config(6144000);
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = "gale",
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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struct lb_range *dma;
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dma = (struct lb_range *)lb_new_record(header);
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dma->tag = LB_TAG_DMA;
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dma->size = sizeof(*dma);
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dma->range_start = (uintptr_t)_dma_coherent;
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dma->range_size = REGION_SIZE(dma_coherent);
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if (CONFIG(CHROMEOS)) {
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/* Retrieve the switch interface MAC addresses. */
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lb_table_add_macs_from_vpd(header);
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}
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}
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