4dd7d11965
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor CPU Datasheet
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* Document number: 575683
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* Chapter number: 15
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/intel/turbo.h>
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#include <cpu/intel/common/common.h>
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#include <fsp/api.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/msr.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/soc_chip.h>
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#include <types.h>
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static void soc_fsp_load(void)
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{
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fsps_load();
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}
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static void configure_misc(void)
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{
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msr_t msr;
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config_t *conf = config_of_soc();
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Set EIST status */
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cpu_set_eist(conf->eist_enable);
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/* Disable Thermal interrupts */
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msr.lo = 0;
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msr.hi = 0;
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wrmsr(IA32_THERM_INTERRUPT, msr);
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/* Enable package critical interrupt only */
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msr.lo = 1 << 4;
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msr.hi = 0;
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wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
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/* Enable PROCHOT */
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msr = rdmsr(MSR_POWER_CTL);
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msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
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msr.lo |= (1 << 23); /* Lock it */
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wrmsr(MSR_POWER_CTL, msr);
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}
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/* All CPUs including BSP will run the following function. */
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void soc_core_init(struct device *cpu)
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{
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/* Clear out pending MCEs */
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/* TODO(adurbin): This should only be done on a cold boot. Also, some
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* of these banks are core vs package scope. For now every CPU clears
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* every bank. */
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mca_configure();
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/* Enable the local CPU apics */
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enable_lapic_tpr();
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setup_lapic();
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/* Configure Enhanced SpeedStep and Thermal Sensors */
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configure_misc();
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enable_pm_timer_emulation();
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/* Enable Direct Cache Access */
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configure_dca_cap();
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/* Set energy policy */
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set_energy_perf_bias(ENERGY_POLICY_NORMAL);
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/* Enable Turbo */
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enable_turbo();
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}
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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}
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static void post_mp_init(void)
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{
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/* Set Max Ratio */
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cpu_set_max_ratio();
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/*
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* 1. Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing.
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* 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
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* to avoid shutdown hang due to lack of init on certain IP in FSP-S.
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*/
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global_smi_enable_no_pwrbtn();
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}
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static const struct mp_ops mp_ops = {
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/*
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* Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
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* that are set prior to ramstage.
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* Real MTRRs programming are being done after resource allocation.
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*/
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.pre_mp_init = soc_fsp_load,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void soc_init_cpus(struct bus *cpu_bus)
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{
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/* TODO: Handle mp_init_with_smm failure? */
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mp_init_with_smm(cpu_bus, &mp_ops);
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/* Thermal throttle activation offset */
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configure_tcc_thermal_target();
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}
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