4e0ec59255
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
84 lines
2.1 KiB
Makefile
84 lines
2.1 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/intel/common
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bootblock-y += gpio_support.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += lpc_init.c
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bootblock-y += pmutil.c
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bootblock-y += tsc_freq.c
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romstage-y += gpio_support.c
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romstage-y += iosf.c
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romstage-y += memmap.c
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romstage-y += pmutil.c
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romstage-y += smbus.c
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romstage-y += spi.c
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romstage-y += tsc_freq.c
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postcar-y += memmap.c
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postcar-y += iosf.c
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postcar-y += spi.c
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postcar-y += tsc_freq.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += emmc.c
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ramstage-y += gpio.c
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ramstage-y += gfx.c
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ramstage-y += gpio_support.c
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ramstage-y += iosf.c
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ramstage-y += lpe.c
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ramstage-y += lpss.c
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ramstage-y += memmap.c
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ramstage-y += northcluster.c
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ramstage-y += pcie.c
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ramstage-y += pmutil.c
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ramstage-y += ramstage.c
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ramstage-y += sata.c
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ramstage-y += scc.c
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ramstage-y += sd.c
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ramstage-y += smm.c
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ramstage-y += southcluster.c
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ramstage-y += spi.c
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ramstage-y += tsc_freq.c
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ramstage-y += xhci.c
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# Remove as ramstage gets fleshed out
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ramstage-y += placeholders.c
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smm-y += lpc_init.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += spi.c
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smm-y += tsc_freq.c
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verstage-y += pmutil.c
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verstage-y += tsc_freq.c
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CPPFLAGS_common += -I$(src)/soc/intel/braswell/
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CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
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CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH))
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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ifneq ($(CONFIG_VGA_BIOS_FILE),)
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#we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
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BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))
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cbfs-files-$(CONFIG_VGA_BIOS) += pci8086,22b1.rom
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pci8086,22b1.rom-file := $(BRASWELL_C0_VBIOS)
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pci8086,22b1.rom-type := optionrom
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endif # ifneq ($(CONFIG_VGA_BIOS_FILE),)
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endif # ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
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