4e9bb3308e
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
46 lines
1.1 KiB
Plaintext
46 lines
1.1 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpigen_extern.asl>
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#if CONFIG(CHROMEOS_NVS)
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/gnvs.asl>
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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/* Operating system enumeration. */
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Name (OSYS, 0)
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/* Zero => PIC mode, One => APIC Mode */
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Name (PICM, Zero)
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/* Power state (AC = 1) */
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Name (PWRS, One)
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/*
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* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method (_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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PICM = Arg0
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}
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#if CONFIG(ECAM_MMCONF_SUPPORT)
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Scope(\_SB) {
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/* Base address of PCIe config space */
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Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
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/* Length of PCIe config space, 1MB each bus */
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Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
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/* PCIe Configuration Space */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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}
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#endif
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